公开(公告)号：US12261222B2

公开(公告)日：2025-03-25

申请号：US18500392

申请日：2023-11-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Neil Quinn Murray ,  Katherine H. Chiang ,  Chung-Te Lin

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/786

Abstract: The present disclosure relates to a method of manufacturing a semiconductor structure. The method may be performed by forming a first source/drain region. A first dielectric layer is formed above the first source/drain region. A portion of the first dielectric layer is removed. A channel region is formed along a sidewall of the first dielectric layer. A gate region is formed along a sidewall of the channel region. A second dielectric layer is formed above the first dielectric layer and the gate region. A portion of the second dielectric layer is removed to form an opening that exposes the channel region. A second source/drain region is formed within the opening.

公开(公告)号：US20250070025A1

公开(公告)日：2025-02-27

申请号：US18943866

申请日：2024-11-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Shyue Lai ,  Chien-Hao Huang ,  Chia-Yu Ling ,  Katherine H CHIANG ,  Chung-Te Lin

IPC: H01L23/528 ,  H01L23/522 ,  H10B51/20 ,  H10B51/30

Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. A memory device is formed in an interconnect structure over a substrate. Forming the memory device includes forming an alternating stack of dielectric material layers and conductive material layers, wherein the alternating stack includes a memory array region and a staircase region adjacent to the memory array region; forming a trench on the memory array region of the alternating stack; forming a data storage layer, channel layers, bit line pillars, and source line pillars in the trench; and performing patterning processes to from a staircase structure on the staircase region. The staircase structure steps downward from a first direction and makes a 180-degree turn to step downward in a second direction opposite to the first direction.

公开(公告)号：US12232329B2

公开(公告)日：2025-02-18

申请号：US18359248

申请日：2023-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H10B51/30

Abstract: The present disclosure relates to an integrated circuit (IC) in which a memory structure comprises a ferroelectric structure without critical-thickness limitations. The memory structure comprises a first electrode and the ferroelectric structure. The ferroelectric structure is vertically stacked with the first electrode and comprises a first ferroelectric layer, a second ferroelectric layer, and a first restoration layer. The second ferroelectric layer overlies the first ferroelectric layer, and the first restoration layer is between and borders the first and second ferroelectric layers. The first restoration layer is a different material type than that of the first and second ferroelectric layers and is configured to decouple crystalline lattices of the first and second ferroelectric layers so the first and second ferroelectric layers do not reach critical thicknesses. A critical thickness corresponds to a thickness at and above which the orthorhombic phase becomes thermodynamically unstable, such that remanent polarization is lost.

公开(公告)号：US20250048742A1

公开(公告)日：2025-02-06

申请号：US18921290

申请日：2024-10-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Katherine H. Chiang ,  Chung-Te Lin

IPC: H01L27/12 ,  H01L29/786 ,  H10B99/00

Abstract: A memory device includes a plurality of memory cells. A first memory cell of the plurality of memory cells includes a first write transistor includes a first write gate, a first write source, and a first write drain. A first read transistor includes first read gate, a first read source, a first read drain, and a first body region separating the first read source from the first read drain. The first read source is coupled to the first write source. A first capacitor has a first upper capacitor plate coupled to the first write drain and a first lower capacitor plate coupled to the first body region of the first read transistor.

公开(公告)号：US20250038124A1

公开(公告)日：2025-01-30

申请号：US18226849

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chang Chiang ,  Katherine Chiang ,  Chung-Te Lin

IPC: H01L23/552 ,  H01L29/786

Abstract: A transistor comprises a colored light shielding layer over the semiconductor layer thereof. The colored light shielding layer reduces exposure of the semiconductor layer to radiation having a wavelength of about 10 nanometers (nm) to about 400 nm. The colored light shielding layer may have a white, black, red, yellow, or gray color. The colored light shielding layer can be formed from a metal oxide film, a p-type oxide semiconductor, or a perovskite. The colored light shielding layer reduces defects that may be generated in the semiconductor layer due to UV light exposure during the manufacturing process, improving device performance and reliability.

公开(公告)号：US12176022B2

公开(公告)日：2024-12-24

申请号：US17878200

申请日：2022-08-01

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Chen-Jun Wu ,  Yun-Feng Kao ,  Sheng-Chih Lai ,  Katherine H. Chiang ,  Chung-Te Lin

IPC: G11C11/4096

Abstract: Disclosed herein are related to a memory device. In one aspect, the memory device includes a memory array including a set of memory cells. In one aspect, each of the set of memory cells includes a corresponding transistor and a corresponding capacitor connected in series between a bit line and a select line. In one aspect, the memory device includes a first transistor including a source/drain electrode coupled to a controller and another source/drain electrode coupled to the bit line. In one aspect, the memory device includes a second transistor including a gate electrode coupled to the bit line. In one aspect, the second transistor is configured to conduct current corresponding to data stored by a memory cell of the set of memory cells.

公开(公告)号：US20240410854A1

公开(公告)日：2024-12-12

申请号：US18333485

申请日：2023-06-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-Che Lee ,  Huai-Ying Huang ,  Yen-Chieh Huang ,  Kai-Wen Cheng ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: G01N27/414 ,  G01N33/00 ,  H01L23/528

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a semiconductor substrate, a hydrogen sensing stacked layer disposed over the semiconductor substrate, and a protection layer disposed on the hydrogen sensing stacked layer. The hydrogen sensing stacked layer comprises a hydrogen-free oxide layer and a metal oxide layer disposed on the hydrogen-free oxide layer.

公开(公告)号：US12167609B2

公开(公告)日：2024-12-10

申请号：US17589634

申请日：2022-01-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Min-Kun Dai ,  Yen-Chieh Huang ,  Kuo-Chang Chiang ,  Han-Ting Tsai ,  Tsann Lin ,  Chung-Te Lin

IPC: H10B51/30 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.

公开(公告)号：US12154965B2

公开(公告)日：2024-11-26

申请号：US17882034

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L51/30 ,  H10B51/20 ,  H10B51/30

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tunning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.

公开(公告)号：US20240387685A1

公开(公告)日：2024-11-21

申请号：US18786081

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30

Abstract: The present disclosure relates to an integrated circuit (IC) chip including a memory cell with a carrier barrier layer for threshold voltage tuning. The memory cell may, for example, include a gate electrode, a ferroelectric structure, and a semiconductor structure. The semiconductor structure is vertically stacked with the gate electrode and the ferroelectric structure, and the ferroelectric structure is between the gate electrode and the semiconductor structure. A pair of source/drain electrodes is laterally separated and respectively on opposite sides of the gate electrode, and a carrier barrier layer separates the source/drain electrodes from the semiconductor structure.