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    MEMORY CELL WITH UNIPOLAR SELECTORS
    2.
    发明申请
    MEMORY CELL WITH UNIPOLAR SELECTORS 有权

    公开(公告)号：US20250120093A1

    公开(公告)日：2025-04-10

    申请号：US18981800

    申请日：2024-12-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Katherine H. Chiang ,  Chung-Te Lin ,  Mauricio Manfrini

    IPC: H10B61/00 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a memory device disposed within an inter-level dielectric (ILD) structure over a substrate. The memory device has a data storage structure between a first electrode and a second electrode. A first unidirectional current controller and a second unidirectional current controller are disposed within the ILD structure. A conductor arranged between the first unidirectional current controller and the data storage structure along a first conductive path and further arranged between the second unidirectional current controller and the data storage structure along a second conductive path. A part of the first conductive path overlaps a part, but not all, of the second conductive path.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250063720A1

    公开(公告)日：2025-02-20

    申请号：US18449710

    申请日：2023-08-15

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： I-Che Lee ,  Huai-Ying Huang ,  Yen-Chieh Huang ,  Wei-Gang Chiu ,  Kai-Wen Cheng ,  Yu-Ming Lin ,  Chung-Te Lin

    IPC: H10B12/00

    Abstract: A semiconductor device includes a substrate, an interconnect, a memory cell, and a plurality of first barrier structures. The interconnect is disposed over the substrate. The memory cell is disposed in the interconnect within a memory region of the substrate, where the memory cell includes a transistor and a capacitor. The transistor includes a gate, source/drain elements respectively standing at two opposite sides of the gate, and a channel disposed between the source/drain elements and overlapped with the gate. The capacitor is disposed over the transistor and electrically coupled to one of the source/drain elements. The plurality of first barrier structures line sidewalls and bottom surfaces of the source/drain elements, and each include a first barrier layer and a second barrier layer disposed between the source/drain elements and the first barrier layer, where a first absorption interface is disposed between the first barrier layer and the second barrier layer.

    METHOD OF FORMING MEMORY DEVICE
    7.
    发明申请
    METHOD OF FORMING MEMORY DEVICE 有权

    公开(公告)号：US20250008738A1

    公开(公告)日：2025-01-02

    申请号：US18885757

    申请日：2024-09-16

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chieh-Fang Chen ,  Feng-Cheng Yang ,  Chung-Te Lin

    IPC: H10B51/20 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10

    Abstract: A memory device includes a plurality of first conductive pillars, a plurality of second conductive pillars, a plurality of gap filling pillars, a channel layer and first dielectric pillars. The gap filling pillars are located in between the first conductive pillars and the second conductive pillars. The channel layer is extending in a first direction, and located on side surfaces of the first conductive pillars and the second conductive pillars. The first dielectric pillars are located in between the channel layer and the plurality of gap filling pillars, wherein a length of an interface where the first dielectric pillars contact the gap filling pillars along the first direction is different from a length of the gap filling pillars along the first direction.

    EMBEDDED FERROELECTRIC FINFET MEMORY DEVICE
    8.
    发明申请
    EMBEDDED FERROELECTRIC FINFET MEMORY DEVICE 有权

    公开(公告)号：US20240389345A1

    公开(公告)日：2024-11-21

    申请号：US18785892

    申请日：2024-07-26

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Bo-Feng Young ,  Chung-Te Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Sheng-Chih Lai ,  Chih-Yu Chang ,  Han-Jong Chia

    IPC: H10B51/30 ,  G11C11/22 ,  H01L27/12

    Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.

    Embedded ferroelectric FinFET memory device
    9.
    发明授权
    Embedded ferroelectric FinFET memory device 有权

    公开(公告)号：US12150311B2

    公开(公告)日：2024-11-19

    申请号：US18364616

    申请日：2023-08-03

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Bo-Feng Young ,  Chung-Te Lin ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Sheng-Chih Lai ,  Chih-Yu Chang ,  Han-Jong Chia

    IPC: H10B51/30 ,  G11C11/22 ,  H01L27/12

    Abstract: Various embodiments of the present disclosure are directed towards a method of forming a ferroelectric memory device. In the method, a pair of source/drain regions is formed in a substrate. A gate dielectric and a gate electrode are formed over the substrate and between the pair of source/drain regions. A polarization switching structure is formed directly on a top surface of the gate electrode. By arranging the polarization switching structure directly on the gate electrode, smaller pad size can be realized, and more flexible area ratio tuning can be achieved compared to arranging the polarization switching structure under the gate electrode with the aligned sidewall and same lateral dimensions. In addition, since the process of forming gate electrode can endure higher annealing temperatures, such that quality of the ferroelectric structure is better controlled.

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