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公开(公告)号：US12302587B2
公开(公告)日：2025-05-13
申请号：US18484466
申请日：2023-10-11
Inventor： Ji-Feng Ying , Jhong-Sheng Wang , Tsann Lin
IPC: H10B61/00 , G11C11/16 , H01F10/32 , H01F41/32 , H01L23/522 , H01L23/528 , H10N50/01 , H10N50/80
Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.
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公开(公告)号：US20240324244A1
公开(公告)日：2024-09-26
申请号：US18679533
申请日：2024-05-31
Inventor： Tsann Lin , Chien-Min Lee , Ji-Feng Ying
Abstract: Some embodiments relate to an integrated chip including a bottom electrode over a semiconductor substrate. A seed layer overlies the bottom electrode. A data storage structure is arranged on the seed layer. A first buffer layer is arranged between the bottom electrode and the seed layer. The first buffer layer is in physical contact with the seed layer and opposing sidewalls of the first buffer layer are aligned with opposing sidewalls of the seed layer.
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公开(公告)号：US11842757B2
公开(公告)日：2023-12-12
申请号：US18077536
申请日：2022-12-08
Inventor： Tsann Lin , Ji-Feng Ying , Chih-Chung Lai
IPC: G11C11/16 , H01L43/10 , H01F10/32 , H01F41/34 , H01L27/22 , H01L43/02 , H01L43/12 , H10B61/00 , H10N50/01 , H10N50/80 , H10N50/85
CPC classification number: G11C11/161 , H01F10/3259 , H01F10/3286 , H01F41/34 , H10B61/22 , H10N50/01 , H10N50/80 , H10N50/85
Abstract: Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
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公开(公告)号：US11672185B2
公开(公告)日：2023-06-06
申请号：US17516469
申请日：2021-11-01
Inventor： Ji-Feng Ying , Jhong-Sheng Wang , Tsann Lin
CPC classification number: H01L43/02 , G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , H01F10/329 , H01F10/3254 , H01L27/228 , H01L43/10 , H01L43/12 , H01L43/04
Abstract: A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.
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公开(公告)号：US20210390992A1
公开(公告)日：2021-12-16
申请号：US16902218
申请日：2020-06-15
Inventor： Jui-Fen Chien , Hanwen Yeh , Tsann Lin
Abstract: A method for forming a semiconductor memory structure is provided. The method includes following operations. An interlayer is formed over a first ferromagnetic layer, wherein forming the interlayer includes following operations. A first metal film is formed by sputtering a first target material. A first oxygen treatment is conducted to the first metal film to form a first metal oxide film. A second metal oxide film is formed over the first metal oxide film by sputtering a second target material different from the first target material. A second metal film is formed by sputtering a third target material. A second oxygen treatment is conducted to the second metal film to form a third metal oxide film.
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Patent Agency Ranking
公开(公告)号：US12274068B2
公开(公告)日：2025-04-08
申请号：US17740331
申请日：2022-05-09
Inventor： Rainer Yen-Chieh Huang , Han-Ting Tsai , Tsann Lin , Kuo-Chang Chiang , Min-Kun Dai , Chung-Te Lin
Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.
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公开(公告)号：US12167609B2
公开(公告)日：2024-12-10
申请号：US17589634
申请日：2022-01-31
Inventor： Min-Kun Dai , Yen-Chieh Huang , Kuo-Chang Chiang , Han-Ting Tsai , Tsann Lin , Chung-Te Lin
IPC: H10B51/30 , H01L21/28 , H01L29/66 , H01L29/78 , H01L29/786
Abstract: A method of forming a semiconductor structure includes following operations. A memory layer is formed over the first gate electrode. A channel layer is formed over the memory layer. A first SUT treatment is performed. A second dielectric layer is formed over the memory layer and the channel layer. A source electrode and a drain electrode are formed in the second dielectric layer. A temperature of the first SUT treatment is less than approximately 400° C.
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公开(公告)号：US12022743B2
公开(公告)日：2024-06-25
申请号：US17395962
申请日：2021-08-06
Inventor： Tsann Lin , Ya-Ling Lee
CPC classification number: H10N50/80 , H10B61/22 , H10N50/01 , H10N50/85 , H01F10/3286
Abstract: A magnetic tunnel junction (MTJ) element is provided. The MTJ element includes a buffer layer, a seed layer disposed over the buffer layer, a reference layer disposed over the seed layer, a tunnel barrier layer disposed over the reference layer and a free layer disposed over the tunnel barrier layer. The seed layer includes a Cobalt (Co)-based film. The MTJ element in accordance with the present disclosure exhibits a low resistance desired for a low-power write operation, and a high TMR coefficient desired for a low bit-error-rate (BER) read operation.
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公开(公告)号：US20240040801A1
公开(公告)日：2024-02-01
申请号：US18484466
申请日：2023-10-11
Inventor： Ji-Feng Ying , Jhong-Sheng Wang , Tsann Lin
IPC: H10B61/00 , H01L23/528 , H01F10/32 , H01L23/522 , H01F41/32 , G11C11/16 , H10N50/01 , H10N50/80
CPC classification number: H10B61/22 , H01L23/528 , H01F10/3259 , H01L23/5226 , H01F10/329 , H01F41/32 , G11C11/161 , H10N50/01 , H10N50/80
Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.
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公开(公告)号：US20230363173A1
公开(公告)日：2023-11-09
申请号：US17740331
申请日：2022-05-09
Inventor： Rainer Yen-Chieh Huang , Han-Ting Tsai , Tsann Lin , Kuo-Chang Chiang , Min-Kun Dai , Chung-Te Lin
IPC: H01L27/1159
CPC classification number: H01L27/1159
Abstract: Provided is a method of forming a ferroelectric memory device including: forming a ferroelectric layer between a gate electrode and a channel layer by a first atomic layer deposition (ALD) process. The first ALD process includes: providing a first precursor during a first section; and providing a first mixed precursor during a second section, wherein the first mixed precursor includes a hafnium-containing precursor and a zirconium-containing precursor. In this case, the ferroelectric layer is directly formed as Hf0.5Zr0.5O2 with an orthorhombic phase (O-phase) to enhance the ferroelectric polarization and property.
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