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公开(公告)号：US20240363765A1
公开(公告)日：2024-10-31
申请号：US18306488
申请日：2023-04-25
发明人： Gerben Doornbos , Georgios Vellianitis , Marcus Johannes Henricus Van Dal , Yu-Ming Lin , Oreste Madia
IPC分类号： H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7883 , H01L29/40114 , H01L29/42324 , H01L29/66825
摘要： Some embodiments relate to an integrated device, including a control gate over a substrate, the control gate having a first length; a tunnel dielectric on the control gate; a floating gate having a second length on the tunnel dielectric, the tunnel dielectric separating the control gate and the floating gate; a blocking dielectric on the floating gate; a channel on the blocking dielectric, the blocking dielectric separating the channel and the floating gate; and source/drain terminals on the channel, wherein the first length of the control gate is less than the second length of the floating gate.
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公开(公告)号：US20240357826A1
公开(公告)日：2024-10-24
申请号：US18757483
申请日：2024-06-27
发明人： Chao-I Wu , Yu-Ming Lin , Sai-Hooi Yeong , Han-Jong Chia
IPC分类号： H10B51/10 , H01L21/28 , H01L23/522 , H01L29/51 , H01L29/66 , H01L29/78 , H10B51/20 , H10B51/30
CPC分类号： H10B51/10 , H01L23/5226 , H01L29/40111 , H01L29/516 , H01L29/66666 , H01L29/78391 , H10B51/20 , H10B51/30
摘要： Provided are a memory device and a method of forming the same. The memory device includes a first tier on a substrate and a second tier on the first tier. The first tier includes a first layer stack; a first gate electrode penetrating through the first layer stack; a first channel layer between the first layer stack and the first gate electrode; and a first ferroelectric layer between the first channel layer and the first gate electrode. The second tier includes a second layer stack; a second gate electrode penetrating through the second layer stack; a second channel layer between the second layer stack and the second gate electrode; and a second ferroelectric layer between the second channel layer and the second gate electrode.
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公开(公告)号：US12114506B2
公开(公告)日：2024-10-08
申请号：US18357139
申请日：2023-07-23
发明人： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
IPC分类号： H10B51/20 , G11C5/06 , G11C11/22 , H01L23/522
CPC分类号： H10B51/20 , G11C5/06 , G11C11/223 , H01L23/5221
摘要： A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.
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公开(公告)号：US20240321637A1
公开(公告)日：2024-09-26
申请号：US18652803
申请日：2024-05-01
发明人： Chia-Lin Chuang , Chia-Hao Chang , Sheng-Tsung Wang , Lin-Yu Huang , Tien-Lu Lin , Yu-Ming Lin , Chih-Hao Wang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L21/76897 , H01L21/76816 , H01L23/5226 , H01L23/5283
摘要： The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
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公开(公告)号：US20240315033A1
公开(公告)日：2024-09-19
申请号：US18677954
申请日：2024-05-30
发明人： Chun-Chieh Lu , Sai-Hooi Yeong , Yu-Ming Lin
IPC分类号： H10B43/27 , H01L23/522 , H10B41/10 , H10B41/27 , H10B43/10
CPC分类号： H10B43/27 , H01L23/5221 , H10B41/10 , H10B41/27 , H10B43/10
摘要： A process of forming a three-dimensional (3D) memory array includes forming a stack having a plurality of conductive layers of carbon-based material separated by dielectric layers. Etching trenches in the stack divides the conductive layers into conductive strips. The resulting structure includes a two-dimensional array of horizontal conductive strips. Memory cells may be distributed along the length of each strip to provide a 3D array. The conductive strips together with additional conductive structure that may have a vertical or horizontal orientation allow the memory cells to be addressed individually. Forming the conductive layers with carbon-based material facilitate etching the trenches to a high aspect ratio. Accordingly, forming the conductive layers of carbon-based material enables the memory array to have more layers or to have a higher area density.
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公开(公告)号：US12089414B2
公开(公告)日：2024-09-10
申请号：US17400081
申请日：2021-08-11
发明人： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
CPC分类号： H10B51/20 , G11C5/06 , G11C11/223
摘要： Provided are a memory device and a method of forming the same. The memory device includes a substrate, a multi-layer stack, a plurality of memory cells, and a plurality of conductive contacts. The substrate includes an array region and a staircase region. The multi-layer stack is disposed on the substrate in the array region, wherein the multi-layer stack has an end portion extending on the staircase region to be shaped into a staircase structure. The plurality of memory cells are respectively disposed on sidewalls of the multi-layer stack in the array region, and arranged at least along a stacking direction of the multi-layer stack. The plurality of conductive contacts are respectively on the staircase structure. At least two conductive contacts are electrically connected to each other.
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公开(公告)号：US20240276738A1
公开(公告)日：2024-08-15
申请号：US18644664
申请日：2024-04-24
发明人： Bo-Feng Young , Sheng-Chen Wang , Sai-Hooi Yeong , Yu-Ming Lin , Mauricio Manfrini , Han-Jong Chia
IPC分类号： H10B63/00 , H01L29/24 , H01L29/66 , H01L29/786 , H10B61/00
CPC分类号： H10B63/30 , H01L29/24 , H01L29/66969 , H01L29/7869 , H10B61/22
摘要： The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.
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公开(公告)号：US20240251564A1
公开(公告)日：2024-07-25
申请号：US18593959
申请日：2024-03-03
发明人： Sheng-Chen Wang , Meng-Han Lin , Sai-Hooi Yeong , Yu-Ming Lin , Han-Jong Chia
IPC分类号： H10B51/20 , H01L29/417 , H10B51/00 , H10B51/10 , H10B51/30
CPC分类号： H10B51/20 , H01L29/41741 , H01L29/41775 , H10B51/00 , H10B51/10 , H10B51/30
摘要： A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and conductive pillars. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.
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公开(公告)号：US11997854B2
公开(公告)日：2024-05-28
申请号：US17749190
申请日：2022-05-20
发明人： Chih-Yu Chang , Sai-Hooi Yeong , Yu-Ming Lin , Chih-Hao Wang
摘要： The present disclosure provides a method for manufacturing a semiconductor structure. The method includes: receiving a substrate; forming a transistor surrounded by a dielectric layer over the substrate, wherein the dielectric layer includes a through hole, and the transistor is formed in the through hole; forming a gate contact in the through hole to electrically connect the transistor; forming a ferroelectric layer over the gate contact in the through hole; forming an insulating layer conformal to and over the dielectric layer and the ferroelectric layer; removing a portion of the insulating layer to form a spacer in the through hole and over the ferroelectric layer; and forming a top electrode over the ferroelectric layer and between the spacer.
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公开(公告)号：US20240128378A1
公开(公告)日：2024-04-18
申请号：US18161855
申请日：2023-01-30
发明人： Yi-Cheng Chu , Chien-Hua Huang , Yu-Ming Lin , Chung-Te Lin
IPC分类号： H01L29/786 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78696 , H01L29/401 , H01L29/41733 , H01L29/42384 , H01L29/66742
摘要： A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.
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