公开(公告)号：US20240274705A1

公开(公告)日：2024-08-15

申请号：US18625366

申请日：2024-04-03

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  B82Y30/00 ,  B82Y40/00 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  B82Y30/00 ,  B82Y40/00

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US11978790B2

公开(公告)日：2024-05-07

申请号：US17108892

申请日：2020-12-01

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  B82Y30/00 ,  B82Y40/00

CPC classification number: H01L29/7786 ,  H01L29/2003 ,  H01L29/66462 ,  B82Y30/00 ,  B82Y40/00

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US20240120383A1

公开(公告)日：2024-04-11

申请号：US18543738

申请日：2023-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/2003

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US20230068191A1

公开(公告)日：2023-03-02

申请号：US18048167

申请日：2022-10-20

Applicant: Texas Instruments Incorporated

Inventor： Nicholas Stephen Dellas ,  Dong Seup Lee ,  Andinet Tefera Desalegn

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L29/205 ,  H01L29/207 ,  H01L29/06

Abstract: In a described example, an integrated circuit (IC) is disclosed that includes a transistor. The transistor includes a substrate, and a buffer structure overlying the substrate. The buffer structure has a first buffer layer, a second buffer layer overlying the first buffer layer, and a third buffer layer overlying the second buffer layer. The first buffer layer has a first carbon concentration, the second buffer layer has a second carbon concentration lower than the first carbon concentration, and the third buffer layer has a third carbon concentration higher than the second carbon concentration. An active structure overlies the buffer structure.

公开(公告)号：US20220173234A1

公开(公告)日：2022-06-02

申请号：US17108892

申请日：2020-12-01

Applicant: Texas Instruments Incorporated

Inventor： Chang Soo Suh ,  Jungwoo Joh ,  Dong Seup Lee ,  Shoji Wada ,  Karen Hildegard Ralston Kirmse

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A semiconductor device includes a gallium nitride based low threshold depletion mode transistor (GaN FET) with a threshold potential between −10 volts and −0.5 volts. The GaN FET has a channel layer of III-N semiconductor material including gallium and nitrogen that supports a two-dimensional electron gas (2 DEG). The GaN FET has a barrier layer of III-N semiconductor material including aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material including gallium and nitrogen. A bottom surface of the gate, adjacent to the barrier layer, does not extend past a top surface of the barrier layer, located opposite from the channel layer. The GaN FET is free of a dielectric layer between the gate and the barrier layer.

公开(公告)号：US20220140087A1

公开(公告)日：2022-05-05

申请号：US17085558

申请日：2020-10-30

Applicant: Texas Instruments Incorporated

Inventor： Qhalid RS Fareed ,  Dong Seup Lee ,  Nicholas S. Dellas

IPC: H01L29/15 ,  H01L21/02

Abstract: Fabrication methods and gallium nitride transistors, in which an electronic device includes a substrate, a buffer structure, a hetero-epitaxy structure over the buffer structure, and a transistor over or in the hetero-epitaxy structure. In one example, the buffer structure has an extrinsically carbon doped gallium nitride layer over a dual superlattice stack or over a multilayer composition graded aluminum gallium nitride stack, and a silicon nitride cap layer over the hetero-epitaxy structure.

公开(公告)号：US10707324B2

公开(公告)日：2020-07-07

申请号：US16456040

申请日：2019-06-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Dong Seup Lee ,  Jungwoo Joh ,  Naveen Tipirneni ,  Sameer Prakash Pendharkar

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L23/535 ,  H01L29/20 ,  H01L27/07 ,  H01L27/088

Abstract: One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.