公开(公告)号：US11888027B2

公开(公告)日：2024-01-30

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/00 ,  H01L29/08 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/2003

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US10529561B2

公开(公告)日：2020-01-07

申请号：US14981348

申请日：2015-12-28

Applicant: Texas Instruments Incorporated

Inventor： Asad Mahmood Haider ,  Qhalid Fareed

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/43 ,  H01L29/778 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/085 ,  H01L29/10 ,  H01L27/088

Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a root mean square (rms) roughness of ) 2 nm deep less than (

公开(公告)号：US20180277535A1

公开(公告)日：2018-09-27

申请号：US15988618

申请日：2018-05-24

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Naveen Tipirneni

IPC: H01L27/088 ,  H01L27/06 ,  H01L29/66 ,  H01L29/778 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/423 ,  H01L29/205

CPC classification number: H01L27/0883 ,  H01L21/02241 ,  H01L21/30612 ,  H01L21/30621 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device containing an enhancement mode GaN FET on a III-N layer stack includes a low-doped GaN layer, a barrier layer including aluminum over the low-doped GaN layer, a stressor layer including indium over the barrier layer, and a cap layer including aluminum over the stressor layer. A gate recess extends through the cap layer and the stressor layer, but not through the barrier layer. The semiconductor device is formed by forming the barrier layer with a high temperature MOCVD process, forming the stressor layer with a low temperature MOCVD process and forming the cap layer with a low temperature MOCVD process. The gate recess is formed by a two-step etch process including a first etch step to remove the cap layer, and a second etch step to remove the stressor layer.

公开(公告)号：US09847223B2

公开(公告)日：2017-12-19

申请号：US15414224

申请日：2017-01-24

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Asad Mahmood Haider

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L21/02505 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7781 ,  H01L29/7784 ,  H01L29/7787 ,  H01L29/78

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

公开(公告)号：US12170328B2

公开(公告)日：2024-12-17

申请号：US17121992

申请日：2020-12-15

Applicant: Texas Instruments Incorporated

Inventor： Tatsuya Tominari ,  Nicholas Stephen Dellas ,  Qhalid Fareed

IPC: H01L29/778 ,  H01L29/04 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: A semiconductor device includes a GaN FET on a silicon substrate and a buffer layer of III-N semiconductor material, with a columnar region, a transition region surrounding the columnar region, and an inter-columnar region around the transition region. The columnar region is higher than the inter-columnar region. The GaN FET includes a gate of III-N semiconductor material with a thickness greater than twice the vertical range of the top surface of the buffer layer in the columnar region. A difference between the gate thickness over the columnar region and over the transition region is less than half of the vertical range of the top surface of the buffer layer in the columnar surface. The semiconductor device may be formed by forming a gate layer of III-N semiconductor material over the barrier layer by a gate MOVPE process using a carrier gas that includes zero to 40 percent hydrogen gas.

公开(公告)号：US20240120383A1

公开(公告)日：2024-04-11

申请号：US18543738

申请日：2023-12-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/2003

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US20240105450A1

公开(公告)日：2024-03-28

申请号：US18090766

申请日：2022-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yoganand Saripalli ,  Russell Fields ,  Brian Goodlin ,  Qhalid Fareed

IPC: H01L21/02 ,  C23C16/30 ,  C23C16/44 ,  C30B25/08 ,  C30B29/40 ,  H01J37/32

CPC classification number: H01L21/02661 ,  C23C16/301 ,  C23C16/4405 ,  C30B25/08 ,  C30B29/40 ,  H01J37/32357 ,  H01J37/32862 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0242 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02664 ,  H01J37/32816 ,  H01J2237/332

Abstract: A Group III-V semiconductor device and a method of fabricating the same including an in-situ surface passivation layer. A two-stage cleaning process may be effectuated for cleaning a reactor chamber prior to growing one or more epitaxial layers and forming subsequent surface passivation layers, wherein a first cleaning process may involve a remotely generated plasma containing fluorine-based reactive species for removing SiXNY residual material accumulated in the reactor chamber and/or over any components disposed therein.

公开(公告)号：US20190288089A9

公开(公告)日：2019-09-19

申请号：US15840392

申请日：2017-12-13

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Asad Mahmood Haider

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.

公开(公告)号：US20190181240A1

公开(公告)日：2019-06-13

申请号：US15840392

申请日：2017-12-13

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Asad Mahmood Haider

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/20 ,  H01L29/778

Abstract: Disclosed examples provide methods for fabricating an epitaxial layer stack for a gallium nitride transistor in an integrated circuit, including forming an aluminum nitride layer (AlN) on a substrate with a predetermined resistivity in a processing chamber, forming an aluminum gallium nitride layer (AlGaN) on the AlN layer in the processing chamber, forming a surface layer on the AlGaN layer in the processing chamber, and controlling the processing chamber temperature after forming the surface layer to cool the substrate and the formed layers at a controlled rate to control wafer bow.

公开(公告)号：US09337023B1

公开(公告)日：2016-05-10

申请号：US14570703

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Qhalid Fareed ,  Asad Mahmood Haider

IPC: H01L29/15 ,  H01L21/02 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L21/02505 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/02513 ,  H01L21/0254 ,  H01L29/1066 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/7781 ,  H01L29/7784 ,  H01L29/7787 ,  H01L29/78

Abstract: A method of fabricating a multi-layer epitaxial buffer layer stack for transistors includes depositing a buffer stack on a substrate. A first voided Group IIIA-N layer is deposited on the substrate, and a first essentially void-free Group IIIA-N layer is then deposited on the first voided Group IIIA-N layer. A first high roughness Group IIIA-N layer is deposited on the first essentially void-free Group IIIA-N layer, and a first essentially smooth Group IIIA-N layer is deposited on the first high roughness Group IIIA-N layer. At least one Group IIIA-N surface layer is then deposited on the first essentially smooth Group IIIA-N layer.

Abstract translation: 制造用于晶体管的多层外延缓冲层堆叠的方法包括在衬底上沉积缓冲层。 第一空穴IIIA-N层被沉积在衬底上，然后在第一空穴IIIA-N层上沉积第一基本无空隙的IIIA-N层。 第一高粗糙度组IIIA-N层沉积在第一基本无空隙的IIIA-N族第一层上，并且第一基本上平滑的IIIA-N层沉积在第一高粗糙度IIIA-N层上。 然后将至少一个IIIA-N族表面层沉积在第一基本上平滑的IIIA-N层上。