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    Pipeline protection for CPUs with save and restore of intermediate results
    41.
    发明授权
    Pipeline protection for CPUs with save and restore of intermediate results 有权

    公开(公告)号：US11269650B2

    公开(公告)日：2022-03-08

    申请号：US16685747

    申请日：2019-11-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Timothy D. Anderson ,  Duc Bui ,  Joseph Zbiciak ,  Reid E. Tatge

    IPC: G06F9/38

    Abstract: Techniques related to executing a plurality of instructions by a processor comprising a method for executing a plurality of instructions by a processor. The method comprises detecting a pipeline hazard based on one or more instructions provided for execution by an instruction execution pipeline, beginning execution of an instruction, of the one or more instructions on the instruction execution pipeline, stalling a portion of the instruction execution pipeline based on the detected pipeline hazard, storing a register state associated with the execution of the instruction based on the stalling, determining that the pipeline hazard has been resolved, and restoring the register state to the instruction execution pipeline based on the determination.

    Superimposing butterfly network controls for pattern combinations
    42.
    发明授权
    Superimposing butterfly network controls for pattern combinations 有权

    公开(公告)号：US11221982B2

    公开(公告)日：2022-01-11

    申请号：US16545196

    申请日：2019-08-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Dheera Balasubramanian ,  Joseph Zbiciak ,  Sureshkumar Govindaraj

    IPC: G06F13/42 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F15/78 ,  G06F12/0875 ,  H04N19/423

    Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

    VECTOR BIT TRANSPOSE
    43.
    发明申请
    VECTOR BIT TRANSPOSE 有权

    公开(公告)号：US20210311736A1

    公开(公告)日：2021-10-07

    申请号：US17353908

    申请日：2021-06-22

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Dheera Balasubramanian Samudrala ,  Duc Bui

    IPC: G06F9/30 ,  G06F7/78

    Abstract: A method to transpose source data in a processor in response to a vector bit transpose instruction includes specifying, in respective fields of the vector bit transpose instruction, a source register containing the source data and a destination register to store transposed data. The method also includes executing the vector bit transpose instruction by interpreting N×N bits of the source data as a two-dimensional array having N rows and N columns, creating transposed source data by transposing the bits by reversing a row index and a column index for each bit, and storing the transposed source data in the destination register.

    TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASIDE BUFFER READ
    45.
    发明申请
    TWO ADDRESS TRANSLATIONS FROM A SINGLE TABLE LOOK-ASIDE BUFFER READ 有权

    公开(公告)号：US20210149820A1

    公开(公告)日：2021-05-20

    申请号：US17158095

    申请日：2021-01-26

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Son H. Tran

    IPC: G06F12/1045 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F11/00 ,  G06F11/10 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/0862 ,  G06F12/1009

    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. An address generator produces virtual addresses of data elements. An address translation unit converts these virtual addresses to physical addresses by comparing the most significant bits of a next address N with the virtual address bits of each entry in an address translation table. Upon a match, the translated address is the physical address bits of the matching entry and the least significant bits of address N. The address translation unit can generate two translated addresses. If the most significant bits of address N+1 match those of address N, the same physical address bits are used for translation of address N+1. The sequential nature of the data stream increases the probability that consecutive addresses match the same address translation entry and can use this technique.

    STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART
    46.
    发明申请
    STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART 审中-公开

    公开(公告)号：US20200272541A1

    公开(公告)日：2020-08-27

    申请号：US16808683

    申请日：2020-03-04

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak ,  Timothy Anderson

    IPC: G06F11/10 ,  G06F11/14 ,  G06F9/345 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/38 ,  G06F11/00

    Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

    Data processing apparatus having streaming engine with read and read/advance operand coding
    47.
    发明授权
    Data processing apparatus having streaming engine with read and read/advance operand coding 有权

    公开(公告)号：US10678545B2

    公开(公告)日：2020-06-09

    申请号：US15204243

    申请日：2016-07-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak

    IPC: G06F9/30 ,  G06F9/345 ,  G06F9/38

    Abstract: A streaming engine employed in a digital signal processor specified a fixed data stream. Once started the data stream is read only and cannot be written. Once fetched the data stream is stored in a first-in-first-out buffer for presentation to functional units in the fixed order. Data use by the functional unit is controlled using the input operand fields of the corresponding instruction. A read only operand coding supplies the data an input of the functional unit. A read/advance operand coding supplies the data and also advances the stream to the next sequential data elements. The read only operand coding permits reuse of data without requiring a register of the register file for temporary storage.

    STREAM ENGINE WITH ELEMENT PROMOTION AND DECIMATION MODES
    48.
    发明申请
    STREAM ENGINE WITH ELEMENT PROMOTION AND DECIMATION MODES 审中-公开

    公开(公告)号：US20200174791A1

    公开(公告)日：2020-06-04

    申请号：US16782580

    申请日：2020-02-05

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to operational units for use as operands. A promotion unit optionally increases date element data size by an integral power of 2 either zero filing or sign filling the additional bits. A decimation unit optionally decimates data elements by an integral factor of 2. For ease of implementation the promotion factor must be greater than or equal to the decimation factor.

    Streaming engine with cache-like stream data storage and lifetime tracking
    49.
    发明授权
    Streaming engine with cache-like stream data storage and lifetime tracking 有权

    公开(公告)号：US10592243B2

    公开(公告)日：2020-03-17

    申请号：US16126680

    申请日：2018-09-10

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Joseph Zbiciak

    IPC: G06F9/312 ,  G06F9/34 ,  G06F12/02 ,  G06F11/10 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/0811 ,  G06F9/345 ,  G06F11/00

    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.

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