公开(公告)号：US10911161B2

公开(公告)日：2021-02-02

申请号：US16697236

申请日：2019-11-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Oswal ,  Visvesvaraya Pentakota ,  Jagannathan Venkataraman ,  Jaiganesh Balakrishnan ,  Francesco Dantoni

IPC: H04B17/13 ,  H04B1/04 ,  H04L27/36

Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.

公开(公告)号：US10898087B2

公开(公告)日：2021-01-26

申请号：US15835646

申请日：2017-12-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara Gunturi ,  Jaiganesh Balakrishnan

IPC: A61B5/024 ,  A61B5/00

Abstract: An apparatus to detect a heart rate of a user includes a motion detection circuit configured to generate a motion status signal indicative of a motion status of the user. The apparatus also comprises a filter circuit coupled to the motion detection circuit that is configured to generate a filter circuit output signal based on dynamically variable. The coefficients are dependent on the motion status signal and a first signal received by the filter circuit. The apparatus also comprises a combination circuit coupled to the filter circuit and configured to receive a second signal indicative of the ambient light, the motion of the user, and non-ambient light reflected from the user. The combination circuit is configured to determine a difference between the second signal and the filter circuit output signal to generate a combination circuit output signal.

公开(公告)号：US10897278B2

公开(公告)日：2021-01-19

申请号：US14323241

申请日：2014-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan

IPC: H04B1/12 ,  H04B1/16 ,  H04H40/72 ,  H04B17/318 ,  H04B17/20 ,  H04B17/336 ,  H04B1/10

Abstract: A wireless receiver (10) includes a down converter module (210) operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module (200) having a filter bandwidth and fed by said down converter module (210), and a measurement module (295) operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module (200) responsive to said measurement module (295) to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module (200) is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.

公开(公告)号：US20200301666A1

公开(公告)日：2020-09-24

申请号：US16852710

申请日：2020-04-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Suvam Nandi ,  Pooja Sundar ,  Jaiganesh Balakrishnan

IPC: G06F7/523 ,  G06F7/50 ,  H03D7/16

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

公开(公告)号：US10396829B2

公开(公告)日：2019-08-27

申请号：US16110478

申请日：2018-08-23

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Suvam Nandi ,  Sundarrajan Rangachari

IPC: G06F17/17 ,  H04B1/00 ,  H04B1/04 ,  H04B1/10 ,  G06F5/01 ,  H03H17/02 ,  H03H17/06

Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.

公开(公告)号：US10341953B2

公开(公告)日：2019-07-02

申请号：US15727891

申请日：2017-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi

IPC: H04L5/12 ,  H04W52/02 ,  H04B1/16 ,  H04L27/26 ,  H04W84/12

Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.

公开(公告)号：US10277202B2

公开(公告)日：2019-04-30

申请号：US15645647

申请日：2017-07-10

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sthanunathan Ramakrishnan ,  Pooja Sundar ,  Sashidharan Venkatraman

IPC: H03H17/02 ,  H03H17/00 ,  G06F5/01 ,  G06F7/544 ,  H03H17/06 ,  H03M1/06 ,  H03M1/12

Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

公开(公告)号：US20160344400A1

公开(公告)日：2016-11-24

申请号：US15145375

申请日：2016-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sthanunathan Ramakrishnan ,  Sashidharan Venkatraman ,  Jaiganesh Balakrishnan

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

CPC classification number: H03M1/0626 ,  H03M1/1009 ,  H03M1/1215

Abstract: Methods, apparatus, systems and articles of manufacture to increase an integrity of mismatch corrections in an interleaved analog to digital converter are disclosed. An example apparatus includes an instantaneous mismatch estimator that uses an output of an interleaved analog to digital converter to identify a mismatch estimate between two or more component analog to digital converters of the interleaved analog to digital converter. An integrity monitor is to cause the instantaneous mismatch estimator to avoid incorrectly providing the mismatch estimate to a filter, the integrity monitor to instruct the filter to remove the mismatch estimate when the mismatch estimate is detected to be inaccurate.

Abstract translation: 公开了用于增加交错模数转换器中的失配校正的完整性的方法，装置，系统和制品。 一个示例性装置包括瞬时失配估计器，其使用交错模数转换器的输出来识别交错模数转换器的两个或多个分量模数转换器之间的失配估计。 完整性监视器是使瞬时失配估计器避免错误地向滤波器提供不匹配估计，当检测到不匹配估计不准确时，完整性监视器指示滤波器去除失配估计。

公开(公告)号：US09491012B1

公开(公告)日：2016-11-08

申请号：US14745349

申请日：2015-06-19

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sriram Murali ,  Sundarrajan Rangachari ,  Sarma Sundareswara Gunturi

IPC: H04L25/03 ,  H04B1/04

CPC classification number: H04L25/03859 ,  H03F1/3241 ,  H04B1/04 ,  H04B1/0475 ,  H04B2001/0425

Abstract: Example embodiments of systems and methods of direct oversampled low PAR pulse shaping encapsulating DSSS spreading are disclosed herein. Pulse-shaping of a DSSS spread data symbol stream results in a small number of waveform patterns to choose from for any data-symbol window. Low complexity programmable look-up table (LUT) based direct pulse shaping may be implemented, while only needing to compute a negation function. The chosen pulse shape may generate a low PAR for the baseband signal, allowing for a reduction in the saturation power of the power amplifier, thereby reducing the overall transmitter power consumption.

Abstract translation: 本文公开了封装DSSS扩展的直接过采样低PAR脉冲整形的系统和方法的示例实施例。 DSSS扩展数据符号流的脉冲整形导致少量波形图案，可供任何数据符号窗口选择。 可以实现基于直接脉冲整形的低复杂度可编程查找表（LUT），而仅需要计算否定函数。 所选择的脉冲形状可以产生用于基带信号的低PAR，允许降低功率放大器的饱和功率，从而降低总的发射机功率消耗。

公开(公告)号：US20140335807A1

公开(公告)日：2014-11-13

申请号：US14323280

申请日：2014-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan

IPC: H04B1/12

CPC classification number: H04B1/12 ,  H04B1/10 ,  H04B1/1027 ,  H04B1/1646 ,  H04B17/20 ,  H04B17/318 ,  H04B17/336 ,  H04B2001/1054 ,  H04H40/72

Abstract: A wireless receiver (10) includes a down converter module (210) operable to deliver a signal having a signal bandwidth that changes over time, a dynamically controllable filter module (200) having a filter bandwidth and fed by said down converter module (210), and a measurement module (295) operable to at least approximately measure the signal bandwidth, said dynamically controllable filter module (200) responsive to said measurement module (295) to dynamically adjust the filter bandwidth to more nearly match the signal bandwidth as it changes over time, whereby output from said filter module (200) is noise-reduced. Other wireless receivers, electronic circuits, and processes for their operation are disclosed.

Abstract translation: 无线接收器（10）包括可转换信号的下变频器模块（210），其具有随时间变化的信号带宽，具有滤波器带宽并由所述下变换器模块（210）馈送的动态可控滤波器模块（200） ，以及可操作以至少近似地测量所述信号带宽的测量模块（295），所述动态可控滤波器模块（200）响应于所述测量模块（295）来动态地调整所述滤波器带宽，使得所述滤波器带宽随着其变化而更接近所述信号带宽 随着时间的推移，来自所述滤波器模块（200）的输出被降噪。 公开了其他无线接收机，电子电路及其操作的处理。