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121 条记录 (耗时 0.042 秒)

    Conduit hanger and support apparatus
    44.
    发明授权
    Conduit hanger and support apparatus 有权
    管道衣架和支撑装置

    公开(公告)号：US08919704B2

    公开(公告)日：2014-12-30

    申请号：US13748656

    申请日：2013-01-24

    申请人： Charles Lee ,  Elio Evangelista ,  Paul Burke

    发明人： Charles Lee ,  Elio Evangelista ,  Paul Burke

    IPC分类号： F16L3/08 ,  F16L3/26

    CPC分类号： F16L3/26 ,  F16L3/11 ,  H02G3/263 ,  Y10T29/49

    摘要： A support assembly for supporting a conduit includes a support, a clamp, and a hanger. The support has a partial-cylindrical shape including a first section having a first diameter and a second section having a second diameter that is greater than the first diameter. In one aspect, at least one of the first section and the second section define a first aperture in the partial-cylindrical shape. In another aspect, at least one of the first section and the second section includes a retention member extending radially from an outer surface of the partial-cylindrical shape. The retention member includes a closed loop or a partially-open loop that defines a second aperture for receiving a strap to secure the conduit to the support. The clamp is configured to secure the conduit to the support. The hanger is configured to suspend the support from a structure.

    摘要翻译： 用于支撑导管的支撑组件包括支撑件，夹具和悬挂器。 支撑件具有部分圆柱形形状，其包括具有第一直径的第一部分和具有大于第一直径的第二直径的第二部分。 在一个方面，第一部分和第二部分中的至少一个限定了部分圆柱形形状的第一孔。 在另一方面，第一部分和第二部分中的至少一个包括从部分圆柱形形状的外表面径向延伸的保持部件。 保持构件包括闭环或部分开放的环，其限定用于接收带以将导管固定到支撑件的第二孔。 夹具被配置成将导管固定到支撑件上。 吊架构造成将结构悬挂在支架上。

    Apparatus for mixing
    45.
    发明授权
    Apparatus for mixing 有权
    混合装置

    公开(公告)号：US08790002B2

    公开(公告)日：2014-07-29

    申请号：US13106292

    申请日：2011-05-12

    申请人： Charles Lee

    发明人： Charles Lee

    IPC分类号： B01F9/08

    CPC分类号： B01F7/1695 ,  B01F3/1221 ,  B01F3/18 ,  B01F7/00141 ,  B01F7/00291 ,  B01F9/0018 ,  B01F9/08 ,  B01F2015/00649

    摘要： An Apparatus for mixing, comprising a tumble-blender adapted to receive and tumble a container to mix the contents of the container. The apparatus includes a drive means for driving a mixer of the container. The drive means is adapted to dock with the mixer when the container is received by the tumble-blender to enable operation of the mixer by the drive means. The drive is movably mounted, relative to the tumble-blender, to facilitate docking of the drive means with the mixer.

    摘要翻译： 一种用于混合的装置，包括适于容纳和滚动容器以混合容器的内容物的滚筒式搅拌器。 该装置包括用于驱动容器的混合器的驱动装置。 驱动装置适于在容器被滚筒式搅拌机接收时与搅拌器对接以使驱动装置能够操作搅拌机。 驱动器相对于滚筒式搅拌器可移动地安装，以便于驱动装置与搅拌器对接。

    Multi-Channel Flash Module with Plane-Interleaved Sequential ECC Writes and Background Recycling to Restricted-Write Flash Chips
    48.
    发明申请
    Multi-Channel Flash Module with Plane-Interleaved Sequential ECC Writes and Background Recycling to Restricted-Write Flash Chips 有权
    具有平面交错顺序ECC的多通道闪存模块写入和背景回收限制写入闪存芯片

    公开(公告)号：US20080034154A1

    公开(公告)日：2008-02-07

    申请号：US11871627

    申请日：2007-10-12

    申请人： Charles Lee ,  Abraham Ma ,  Frank Yu ,  David Chow ,  Ming-Shiang Shen

    发明人： Charles Lee ,  Abraham Ma ,  Frank Yu ,  David Chow ,  Ming-Shiang Shen

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0607 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7203 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C16/0408 ,  G11C2211/5649

    摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.

    摘要翻译： 使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 还执行后台回收和ECC写入。

    Flash Module with Plane-Interleaved Sequential Writes to Restricted-Write Flash Chips
    49.
    发明申请
    Flash Module with Plane-Interleaved Sequential Writes to Restricted-Write Flash Chips 有权
    闪存模块与平面交错顺序写入限制写入闪存芯片

    公开(公告)号：US20080034153A1

    公开(公告)日：2008-02-07

    申请号：US11871011

    申请日：2007-10-11

    申请人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  David Chow ,  Ming-Shiang Shen

    发明人： Charles Lee ,  Frank Yu ,  Abraham Ma ,  David Chow ,  Ming-Shiang Shen

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F12/0607 ,  G06F2212/7201 ,  G06F2212/7208 ,  G11C11/5621 ,  G11C16/0408

    摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.

    摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。 闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。 这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。 物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。 这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

    Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface
    50.
    发明申请
    Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface 失效
    使用串行链路分组接口的多环拓扑中的闪存/相变存储器

    公开(公告)号：US20080016269A1

    公开(公告)日：2008-01-17

    申请号：US11773827

    申请日：2007-07-05

    申请人： David Chow ,  Charles Lee ,  Frank Yu

    发明人： David Chow ,  Charles Lee ,  Frank Yu

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1684 ,  G11C13/0004 ,  G11C16/102 ,  G11C2216/30

    摘要： A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.

    摘要翻译： 多环存储器控制器将请求数据包发送到串行闪存芯片的多个环。 多个环中的每个环都具有串行闪存芯片，其具有单向环中的串行链路。 每个串行闪存芯片都具有一个旁路收发器，其中设备ID检查器将串行数据包绕过时钟重新同步器，并且旁路逻辑用于重传到环中的下一个设备，或者当ID为ID时将串行数据包提取给本地设备 匹配发生。 在来自控制器的一次往返事务期间，串行数据包通过环中的所有设备。 由于相同的数据包延迟发生，环路上的所有设备的平均延迟都是恒定的，从而降低了数据相关性能，无论环的数据位置如何。 串行链路可以是外围组件互连（PCI）Express总线。 数据包已经修改了PCI-Express头，定义了数据包类型和数据有效负载长度。