公开(公告)号：US20150324253A1

公开(公告)日：2015-11-12

申请号：US14728749

申请日：2015-06-02

申请人： California Institute of Technology ,  Texas A&M University System

发明人： Anxiao Jiang ,  Eyal En Gad ,  Jehoshua Bruck ,  Eitan Yaakobi

IPC分类号： G06F11/10 ,  G11C29/52 ,  G11C16/34

CPC分类号： G06F11/1072 ,  G06F11/1016 ,  G06F12/0246 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/349 ,  G11C29/52 ,  G11C2211/5649 ,  H03M13/13

摘要： Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

摘要翻译： 近来已经提出了等级调制作为用于将信息存储在闪速存储器中的方案。 公开了三个改进的方面。 在一个方面，提供了用于将数据存储在闪速存储器中的最小上推方案。 它旨在最大限度地减少改变记忆状态的成本。 在另一方面，提供了用于将数据存储在闪存中的多单元。 每个晶体管被并联连接的mm晶体管的多单元电池代替。 在另一方面，提供了多重排列。 代表具有置换的信息的范例被推广到每个级别中的单元的数量是大于1的常数的情况。 在另一方面，提供利用极性码的秩调制重写方案用于闪速存储器。

公开(公告)号：US20140089560A1

公开(公告)日：2014-03-27

申请号：US13626721

申请日：2012-09-25

申请人： Ravi Sunkavalli ,  Malcolm Wing

发明人： Ravi Sunkavalli ,  Malcolm Wing

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F11/00 ,  G06F11/1072 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/349 ,  G11C29/82 ,  G11C2211/5649

摘要： A memory system can include a plurality of memory elements each comprising a memory layer having at least one layer programmable between at least two different impedance states; a data input configured to receive multi-bit write data values; and a permutation circuit coupled between the memory elements and the data input, and configured to repeatedly permute the multi-bit write data values prior to writing such data values into the memory elements.

摘要翻译： 存储器系统可以包括多个存储器元件，每个存储器元件包括具有在至少两个不同阻抗状态之间可编程的至少一个层的存储器层; 配置为接收多位写数据值的数据输入; 以及置换电路，其耦合在所述存储器元件和所述数据输入之间，并且被配置为在将所述数据值写入所述存储器元件之前重复地排列所述多位写数据值。

公开(公告)号：US07394695B2

公开(公告)日：2008-07-01

申请号：US11511488

申请日：2006-08-29

申请人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

发明人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C7/1051 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5649 ,  G11C2211/565 ,  G11C2216/14

摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

摘要翻译： 具有三个以上值的数据以非易失性方式存储在存储单元中。 数据电路具有多个存储电路。 多个存储电路中的一个是锁存电路。 多个存储电路中的另一个是电容器。 锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。 如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。 结果，即使使用多级数据，数据电路也不会变大。

公开(公告)号：US20130254466A1

公开(公告)日：2013-09-26

申请号：US13791823

申请日：2013-03-08

申请人： CALIFORNIA INSTITUTE OF TECHNOLOGY ,  TEXAS A&M UNIVERSITY SYSTEM

发明人： Anxiao Jiang ,  Eyal En Gad ,  Jehoshua Bruck ,  Eitan Yaakobi

IPC分类号： G06F12/02

CPC分类号： G06F11/1072 ,  G06F11/1016 ,  G06F12/0246 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/349 ,  G11C29/52 ,  G11C2211/5649 ,  H03M13/13

摘要： Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

公开(公告)号：US07768829B2

公开(公告)日：2010-08-03

申请号：US12340290

申请日：2008-12-19

申请人： Noboru Shibata

发明人： Noboru Shibata

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/12 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5648 ,  G11C2211/5649 ,  G11C2211/565

摘要： In a memory cell array, a plurality of memory cells are arranged in a matrix. Each of the plurality of memory cells stores one of a plurality of threshold levels. When writing one of the plurality of threshold levels into a first memory cell of the memory cell array, a control circuit writes a threshold level a little lower than the original threshold level. When not writing a second memory cell adjacent to the first memory cell consecutively, the control circuit writes the original threshold level into the first memory cell.

摘要翻译： 在存储单元阵列中，多个存储单元被布置成矩阵。 多个存储单元中的每一个存储多个阈值水平中的一个。 当将多个阈值电平中的一个写入到存储单元阵列的第一存储单元中时，控制电路写入比原始阈值电平略低的阈值电平。 当不连续地写入与第一存储器单元相邻的第二存储单元时，控制电路将原始阈值电平写入第一存储单元。

公开(公告)号：US20070058433A1

公开(公告)日：2007-03-15

申请号：US11511488

申请日：2006-08-29

申请人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

发明人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C7/1051 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5649 ,  G11C2211/565 ,  G11C2216/14

摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

公开(公告)号：US20020114207A1

公开(公告)日：2002-08-22

申请号：US10073999

申请日：2002-02-14

申请人： Kabushiki Kaisha Toshiba

发明人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

IPC分类号： G11C008/00

CPC分类号： G11C16/3418 ,  G11C7/1051 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5649 ,  G11C2211/565 ,  G11C2216/14

摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

公开(公告)号：US09086955B2

公开(公告)日：2015-07-21

申请号：US13791823

申请日：2013-03-08

申请人： California Institute of Technology ,  Texas A&M University System

发明人： Anxiao Jiang ,  Eyal En Gad ,  Jehoshua Bruck ,  Eitan Yaakobi

IPC分类号： G06F12/02 ,  H03M13/13 ,  G11C16/10 ,  G11C7/10 ,  G11C11/56

CPC分类号： G06F11/1072 ,  G06F11/1016 ,  G06F12/0246 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/349 ,  G11C29/52 ,  G11C2211/5649 ,  H03M13/13

摘要： Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one. In yet another aspect, rank-modulation rewriting schemes which take advantage of polar codes, are provided for use with flash memory.

摘要翻译： 近来已经提出了等级调制作为用于将信息存储在闪速存储器中的方案。 公开了三个改进的方面。 在一个方面，提供了用于将数据存储在闪速存储器中的最小上推方案。 它旨在最大限度地减少改变记忆状态的成本。 在另一方面，提供了用于将数据存储在闪存中的多单元。 每个晶体管被并联连接的mm晶体管的多单元电池代替。 在另一方面，提供了多重排列。 代表具有置换的信息的范例被推广到每个级别中的单元的数量是大于1的常数的情况。 在另一方面，提供利用极性码的秩调制重写方案用于闪速存储器。

公开(公告)号：US07864592B2

公开(公告)日：2011-01-04

申请号：US12551936

申请日：2009-09-01

申请人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

发明人： Ken Takeuchi ,  Tomoharu Tanaka ,  Noboru Shibata

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C7/1051 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5649 ,  G11C2211/565 ,  G11C2216/14

摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

公开(公告)号：US20090323416A1

公开(公告)日：2009-12-31

申请号：US12551936

申请日：2009-09-01

申请人： Ken TAKEUCHI ,  Tomoharu TANAKA ,  Noboru SHIBATA

发明人： Ken TAKEUCHI ,  Tomoharu TANAKA ,  Noboru SHIBATA

IPC分类号： G11C16/04 ,  G11C8/10 ,  G11C8/00

CPC分类号： G11C16/3418 ,  G11C7/1051 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2211/5643 ,  G11C2211/5649 ,  G11C2211/565 ,  G11C2216/14

摘要： Data having three values or more is stored in a memory cell in a nonvolatile manner. A data circuit has a plurality of storage circuits. One of the plurality of storage circuits is a latch circuit. Another one of the plurality of storage circuits is a capacitor. The latch circuit and the capacitor function to temporarily store program/read data having two bits or more. Data held by the capacitor is refreshed using the latch circuit if data variation due to leakage causes a program. As a result, the data circuit does not become large in size even if multi-level data is used.

摘要翻译： 具有三个以上值的数据以非易失性方式存储在存储单元中。 数据电路具有多个存储电路。 多个存储电路中的一个是锁存电路。 多个存储电路中的另一个是电容器。 锁存电路和电容器用于临时存储具有两位或更多位的程序/读数据。 如果由于泄漏引起的数据变化导致程序，则使用锁存电路来刷新由电容器保持的数据。 结果，即使使用多级数据，数据电路也不会变大。