公开(公告)号：US20120142281A1

公开(公告)日：2012-06-07

申请号：US13307417

申请日：2011-11-30

申请人： Tilo Ferchland ,  Katja Schwieger ,  Joerg Wunsch ,  Dietmar Eggert ,  Leslie J. Mulder ,  Fred Fierling

发明人： Tilo Ferchland ,  Katja Schwieger ,  Joerg Wunsch ,  Dietmar Eggert ,  Leslie J. Mulder ,  Fred Fierling

IPC分类号： H04B1/38

CPC分类号： H04L65/104 ,  H04L61/6004 ,  H04L61/6022 ,  H04L61/6081

摘要： In one embodiment, receiving a first radio frequency (RF) signal from a first node, generating a first digital data set by decoding the first received RF signal, determining whether a first address in the first digital data set is associated with at least one of a first radio network or a second radio network by comparing the first address to a first set of addresses associated with the first radio network and a second set of addresses associated with the second radio network, appending a first status to the first digital data set indicating that the first address is associated with the first or second radio network, and transmitting an interrupt signal and the first digital data set to a microcontroller for evaluation by the microcontroller in response to determining that the first address is associated with at least one of the first or second radio network.

摘要翻译： 在一个实施例中，从第一节点接收第一射频（RF）信号，通过解码第一接收的RF信号来产生第一数字数据集，确定第一数字数据集中的第一地址是否与 第一无线电网络或第二无线电网络，通过将第一地址与与第一无线电网络相关联的第一组地址和与第二无线电网络相关联的第二组地址进行比较，将第一状态附加到第一数字数据集，指示 所述第一地址与所述第一或第二无线电网络相关联，并且将中断信号和所述第一数字数据集发送到微控制器以响应于确定所述第一地址与所述第一地址中的至少一个与所述第一地址相关联 或第二无线电网络。

公开(公告)号：US07868679B2

公开(公告)日：2011-01-11

申请号：US12481249

申请日：2009-06-09

申请人： Thorsten Riedel ,  Jeannette Zarbock ,  Tilo Ferchland

发明人： Thorsten Riedel ,  Jeannette Zarbock ,  Tilo Ferchland

IPC分类号： H03H11/26

CPC分类号： H03K3/84

摘要： A circuit is provided that includes an input for a clock signal, a random event generator for outputting a random signal, in particular random numbers, a settable delay device that is connected to the input for the clock signal and is connected to the random event generator for the purpose of setting a delay of an edge of the clock signal (clk) by means of the random signal.

摘要翻译： 提供一种电路，其包括用于时钟信号的输入端，用于输出随机信号，特别是随机数的随机事件发生器，连接到时钟信号的输入并连接到随机事件发生器的可设置延迟器件 用于通过随机信号设置时钟信号（clk）的边沿的延迟。

公开(公告)号：US20090257482A1

公开(公告)日：2009-10-15

申请号：US12423599

申请日：2009-04-14

申请人： Sascha Beyer ,  Tilo Ferchland ,  Thomas Hanusch

发明人： Sascha Beyer ,  Tilo Ferchland ,  Thomas Hanusch

IPC分类号： H04B17/00

CPC分类号： H04B7/204 ,  H04B17/20 ,  H04L1/1867

摘要： A receiving circuit, method for receiving a signal, and use of a detection circuit and a control circuit of a receiving circuit of a node of a radio network is provided to deactivate an analog signal processing and/or determination of digital data from a signal received over an antenna of the node, when a stored current frame of the digital data has been recognized as valid, and to activate the analog signal processing and/or the determination, when the transmission of the current frame over an interface of the control circuit has been confirmed, whereby the control circuit is connected to the detection circuit and/or an input circuit for deactivation and activation, and whereby the detection circuit is formed to determine the digital data from the received signal.

摘要翻译： 提供一种接收电路，用于接收信号的方法，以及使用无线电网络的节点的接收电路的检测电路和控制电路，以从接收到的信号中去激活模拟信号处理和/或确定数字数据 通过节点的天线，当存储的数字数据的当前帧已经被识别为有效时，并且当控制电路的接口上的当前帧的传输具有 由此控制电路连接到检测电路和/或用于去激活和激活的输入电路，由此形成检测电路以根据接收到的信号确定数字数据。

公开(公告)号：US08415939B2

公开(公告)日：2013-04-09

申请号：US13485426

申请日：2012-05-31

申请人： Wolfram Kluge ,  Jeanette Zarbock ,  Tilo Ferchland

发明人： Wolfram Kluge ,  Jeanette Zarbock ,  Tilo Ferchland

IPC分类号： G05F1/44

CPC分类号： G11C5/14 ,  G11C5/143 ,  G11C5/147

摘要： A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.

摘要翻译： 提供了一种用于操作电路的电路和方法，其包括具有多个存储元件的电路部分，可以连接或连接到电路部分以便操作电路部分的第一电压调节器，第二电压调节器 可以连接或连接到电路部分，以便保存存储在存储元件中的信息项，连接到电路部分并被设计为停用和激活电路部分的输入的开关装置。 电路被配置为控制第一电压调节器的去激活和激活以及电路部分的输入的去激活和激活。

公开(公告)号：US20090302821A1

公开(公告)日：2009-12-10

申请号：US12481330

申请日：2009-06-09

申请人： Wolfram KLUGE ,  Jeannette Zarbock ,  Tilo Ferchland

发明人： Wolfram KLUGE ,  Jeannette Zarbock ,  Tilo Ferchland

IPC分类号： G05F3/02

CPC分类号： G11C5/14 ,  G11C5/143 ,  G11C5/147

摘要： A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.

摘要翻译： 提供了一种用于操作电路的电路和方法，其包括具有多个存储元件的电路部分，可以连接或连接到电路部分以便操作电路部分的第一电压调节器，第二电压调节器 可以连接或连接到电路部分，以便保存存储在存储元件中的信息项，连接到电路部分并被设计为停用和激活电路部分的输入的开关装置。 电路被配置为控制第一电压调节器的去激活和激活以及电路部分的输入的去激活和激活。

公开(公告)号：US07190709B2

公开(公告)日：2007-03-13

申请号：US10464960

申请日：2003-06-19

申请人： Uwe Eckhardt ,  Jörg Borowski ,  Tilo Ferchland

发明人： Uwe Eckhardt ,  Jörg Borowski ,  Tilo Ferchland

IPC分类号： H04L27/00

CPC分类号： H04L7/007 ,  H04B1/7085 ,  H04L7/0029

摘要： A timing error correction technique for use in data communications receivers such as WLAN (Wireless Local Area Network) receivers is provided where an input signal is received that has a timing error, the timing error is corrected, and a signal having a corrected timing error is output. The timing error correction comprises performing an early-late correlation on the signal that has the corrected timing error. The early-late correlation comprises the generation of at least one early and late sample pair, the generation of an error signal that is indicative of the difference between the early and late samples, and the generation of at least one control signal based on the error signal. A time offset correction algorithm is performed dependent on the control signal.

摘要翻译： 提供了一种在诸如WLAN（无线局域网）接收机的数据通信接收机中使用的定时误差校正技术，其中接收到具有定时误差的输入信号，定时误差被校正，并且具有校正的定时误差的信号是 输出。 定时误差校正包括对具有校正的定时误差的信号执行早期相关。 早期相关性包括产生至少一个早期和晚期样本对，产生指示早期和晚期样本之间的差异的误差信号，以及基于误差产生至少一个控制信号 信号。 根据控制信号执行时间偏移校正算法。

公开(公告)号：US09054718B2

公开(公告)日：2015-06-09

申请号：US13307561

申请日：2011-11-30

申请人： Tilo Ferchland ,  Sascha Beyer ,  Dietmar Eggert ,  Udo Walter

发明人： Tilo Ferchland ,  Sascha Beyer ,  Dietmar Eggert ,  Udo Walter

IPC分类号： H03L7/183 ,  H04B1/66

CPC分类号： H03L7/183 ,  H04B1/662

摘要： In one embodiment, a transceiver may set a first receive frequency of a first channel of the transceiver and a second receive frequency of a second channel of the transceiver. The transceiver may receive, during a first time interval, a first radio frequency (RF) signal on the first channel. The transceiver may determine that a first measured value indicative of a first detectable received RF signal on the first channel exceeds a first predetermined threshold, and in response, receive a first data frame on the first channel. The transceiver may receive, during a second time interval, a second RF signal on the second channel. The transceiver determine that a second measured value indicative of a second detectable received RF signal on the second channel exceeds the first predetermined threshold, and in response, receive a second data frame on the second channel.

摘要翻译： 在一个实施例中，收发器可以设置收发器的第一通道的第一接收频率和收发器的第二通道的第二接收频​​率。 在第一时间间隔期间，收发机可以在第一信道上接收第一射频（RF）信号。 收发器可以确定指示第一信道上的第一可检测接收RF信号的第一测量值超过第一预定阈值，并且作为响应，在第一信道上接收第一数据帧。 收发机可以在第二时间间隔期间在第二信道上接收第二RF信号。 收发器确定指示第二信道上的第二可检测接收RF信号的第二测量值超过第一预定阈值，并且作为响应，在第二信道上接收第二数据帧。

公开(公告)号：US08755300B2

公开(公告)日：2014-06-17

申请号：US13663187

申请日：2012-10-29

申请人： Eric J. Sachse ,  Tilo Ferchland ,  Wolfram Kluge

发明人： Eric J. Sachse ,  Tilo Ferchland ,  Wolfram Kluge

IPC分类号： H04L12/26

CPC分类号： H04W24/08 ,  G01S5/0289 ,  G01S13/84 ,  H04W24/00

摘要： A first node of a radio network initiates a mode for finding the range to a second node. The first node transmits to the second node, with the address of the second node, a range finding command, which switches the second node into the range finding mode and controls a sequence. The first node transmits in a transmission time window a first signal, which is received by the second node in an associated reception time window, a first phase value of the first signal being measured. The second node transmits in a transmission time window a second signal, which is received by the first node in an associated reception time window, a second phase value of the second signal being measured. The first frequency is changed by a frequency difference and the second frequency is changed by the frequency difference in a subsequent time window of the sequence.

摘要翻译： 无线电网络的第一节点发起用于找到第二节点的范围的模式。 第一节点利用第二节点的地址向第二节点传送测距命令，该命令将第二节点切换到测距模式并控制序列。 第一节点在传输时间窗口中发送由相关联的接收时间窗口中的第二节点接收的被测量的第一信号的第一相位值的第一信号。 第二节点在传输时间窗口中发送由相关联的接收时间窗口中的第一节点接收的被测量的第二信号的第二相位值的第二信号。 第一频率被频率差改变，并且第二频率在序列的后续时间窗中被频率差改变。

公开(公告)号：US08363708B2

公开(公告)日：2013-01-29

申请号：US12423599

申请日：2009-04-14

申请人： Sascha Beyer ,  Tilo Ferchland ,  Thomas Hanusch

发明人： Sascha Beyer ,  Tilo Ferchland ,  Thomas Hanusch

IPC分类号： H04B3/46 ,  H04B17/00 ,  H04Q1/20

CPC分类号： H04B7/204 ,  H04B17/20 ,  H04L1/1867

摘要： A receiving circuit, method for receiving a signal, and use of a detection circuit and a control circuit of a receiving circuit of a node of a radio network is provided to deactivate an analog signal processing and/or determination of digital data from a signal received over an antenna of the node, when a stored current frame of the digital data has been recognized as valid, and to activate the analog signal processing and/or the determination, when the transmission of the current frame over an interface of the control circuit has been confirmed, whereby the control circuit is connected to the detection circuit and/or an input circuit for deactivation and activation, and whereby the detection circuit is formed to determine the digital data from the received signal.

摘要翻译： 提供一种接收电路，用于接收信号的方法，以及使用无线电网络的节点的接收电路的检测电路和控制电路，以从接收到的信号中去激活模拟信号处理和/或确定数字数据 通过节点的天线，当存储的数字数据的当前帧已经被识别为有效时，并且当控制电路的接口上的当前帧的传输具有 由此控制电路连接到检测电路和/或用于去激活和激活的输入电路，由此形成检测电路以根据接收到的信号确定数字数据。

公开(公告)号：US20120236674A1

公开(公告)日：2012-09-20

申请号：US13485426

申请日：2012-05-31

申请人： Wolfram Kluge ,  Jeannette Zarbock ,  Tilo Ferchland

发明人： Wolfram Kluge ,  Jeannette Zarbock ,  Tilo Ferchland

IPC分类号： G11C5/14 ,  G05F1/10

CPC分类号： G11C5/14 ,  G11C5/143 ,  G11C5/147

摘要： A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.

摘要翻译： 提供了一种用于操作电路的电路和方法，其包括具有多个存储元件的电路部分，可以连接或连接到电路部分以便操作电路部分的第一电压调节器，第二电压调节器 可以连接或连接到电路部分，以便保存存储在存储元件中的信息项，连接到电路部分并被设计为停用和激活电路部分的输入的开关装置。 电路被配置为控制第一电压调节器的去激活和激活以及电路部分的输入的去激活和激活。