公开(公告)号：US20170017416A1

公开(公告)日：2017-01-19

申请号：US14829644

申请日：2015-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： ZHIBIAO ZHOU ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F1/3293 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/141 ,  G11C7/1006 ,  G11C16/00 ,  G11C2211/4016 ,  H01L27/06 ,  H01L27/07 ,  H01L27/108

Abstract: A semiconductor device includes a main processor, a normally-off processor, and at least one oxide semiconductor random access memory (RAM). The normally-off processor includes at least one oxide semiconductor transistor. The main processor is connected to the normally-off processor, and a clock rate of the main processor is higher than a clock rate of the normally-off processor. The oxide semiconductor RAM is connected to the normally-off processor. An operating method of the semiconductor includes backing up data from the main processor to the normally-off process and/or the oxide semiconductor RAM.

Abstract translation: 半导体器件包括主处理器，常关处理器和至少一个氧化物半导体随机存取存储器（RAM）。 常关处理器包括至少一个氧化物半导体晶体管。 主处理器连接到常关处理器，并且主处理器的时钟速率高于常关处理器的时钟速率。 氧化物半导体RAM连接到常关处理器。 半导体的操作方法包括将数据从主处理器备份到常关处理和/或氧化物半导体RAM。

公开(公告)号：US09431441B1

公开(公告)日：2016-08-30

申请号：US14834452

申请日：2015-08-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhibiao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu ,  Chia-Fu Hsu

IPC: H01L29/10 ,  H01L27/146 ,  H01L29/786

CPC classification number: H01L27/14612 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14643 ,  H01L29/7869

Abstract: A back side illumination image sensor pixel structure includes a substrate having a front side and a back side opposite to the front side, a sensing device formed in the substrate to receive an incident light through the back side of the substrate, two oxide-semiconductor field effect transistor (OS FET) devices formed on the front side of the substrate, and a capacitor formed on the front side of the substrate. The two OS FET devices are directly stacked on the sensing device and the capacitor is directly stacked on the OS FET devices. The two OS FET devices overlap the sensing device, and the capacitor overlaps both of the OS FET devices and the sensing device.

Abstract translation: 背面照明图像传感器像素结构包括具有与前侧相反的前侧和后侧的基板，形成在基板中以接收穿过基板的背面的入射光的感测装置，两个氧化物半导体场 形成在基板的前侧的效应晶体管（OS FET）器件，以及形成在基板的前侧的电容器。 两个OS FET器件直接堆叠在感测器件上，电容器直接堆叠在OS FET器件上。 两个OS FET器件与感测器件重叠，并且电容器与OS FET器件和感测器件重叠。

公开(公告)号：US09349873B1

公开(公告)日：2016-05-24

申请号：US14825511

申请日：2015-08-13

Applicant: United Microelectronics Corp.

Inventor： Zhi-Biao Zhou ,  Shao-Hui Wu ,  Chi-Fa Ku ,  Chen-Bin Lin ,  Chun-Yuan Wu

IPC: H01L21/441 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/768 ,  H01L29/24

CPC classification number: H01L29/7869 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78648

Abstract: Provided is an oxide semiconductor device. A source, a drain, and a first gate are buried in a first dielectric layer, and the first gate is located between the source and the drain. A first barrier layer is located on the first dielectric layer, partially overlaps the source and the drain and overlaps the first gate. The first barrier layer includes a first opening and a second opening respectively corresponds to the source and the drain. An oxide semiconductor layer covers the first barrier layer and fills in the first opening and the second opening. A second barrier layer is located on the oxide semiconductor layer. A second gate is located on the second barrier layer and overlaps with the source, the drain, and the first gate.

Abstract translation: 提供一种氧化物半导体器件。 源极，漏极和第一栅极被埋在第一电介质层中，并且第一栅极位于源极和漏极之间。 第一阻挡层位于第一电介质层上，部分地与源极和漏极重叠并与第一栅极重叠。 第一阻挡层包括第一开口和第二开口，分别对应于源极和漏极。 氧化物半导体层覆盖第一阻挡层并填充在第一开口和第二开口中。 第二阻挡层位于氧化物半导体层上。 第二栅极位于第二阻挡层上并与源极，漏极和第一栅极重叠。