公开(公告)号：US11925035B2

公开(公告)日：2024-03-05

申请号：US17973557

申请日：2022-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Ju-Chun Fan ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N70/063 ,  H10N70/24 ,  H10N70/826 ,  H10N70/8833

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

公开(公告)号：US20240027549A1

公开(公告)日：2024-01-25

申请号：US18376451

申请日：2023-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Che-Wei Chang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: G01R33/09 ,  G11C11/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G01R33/093 ,  G01R33/098 ,  G11C11/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

公开(公告)号：US11821964B2

公开(公告)日：2023-11-21

申请号：US16927918

申请日：2020-07-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Che-Wei Chang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: G01R33/09 ,  G11C11/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G01R33/093 ,  G01R33/098 ,  G11C11/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

公开(公告)号：US11700775B2

公开(公告)日：2023-07-11

申请号：US17090859

申请日：2020-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Ching-Hua Hsu ,  Hung-Yueh Chen

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：US20230050435A1

公开(公告)日：2023-02-16

申请号：US17973557

申请日：2022-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Ju-Chun Fan ,  Hung-Yueh Chen

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L45/00 ,  H01L43/12 ,  H01L43/08

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.