公开(公告)号：US11955154B2

公开(公告)日：2024-04-09

申请号：US17744746

申请日：2022-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Tung Huang ,  Jen-Yu Wang ,  Po-Chun Yang ,  Yi-Ting Wu ,  Yung-Ching Hsieh ,  Jian-Jhong Chen ,  Chia-Wei Lee

IPC: G11C7/00 ,  G11C11/16

CPC classification number: G11C11/1673

Abstract: A sense amplifier circuit includes a sense amplifier, a switch and a temperature compensation circuit. The temperature compensation circuit provides a control signal having a positive temperature coefficient, based on which the switch provides reference impedance for temperature compensation. The sense amplifier includes a first input end coupled to a target bit and a second input end coupled to the switch. The sense amplifier outputs a sense amplifier signal based on the reference impedance and the impedance of the target bit.

公开(公告)号：US20220020745A1

公开(公告)日：2022-01-20

申请号：US17492687

申请日：2021-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Wei Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yan-Jou Chen

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78

Abstract: A semiconductor device includes a PMOS region and a NMOS region on a substrate, a first fin-shaped structure on the PMOS region, a first single diffusion break (SDB) structure in the first fin-shaped structure, a first gate structure on the first SDB structure, and a second gate structure on the first fin-shaped structure. Preferably, the first gate structure and the second gate structure are of different materials and the first gate structure disposed directly on top of the first SDB structure is a polysilicon gate while the second gate structure disposed on the first fin-shaped structure is a metal gate in the PMOS region.

公开(公告)号：US10483264B2

公开(公告)日：2019-11-19

申请号：US15660970

申请日：2017-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yen-Wei Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yan-Jou Chen

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/02 ,  H01L27/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.

公开(公告)号：US09722093B1

公开(公告)日：2017-08-01

申请号：US15253896

申请日：2016-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L21/28 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11585

CPC classification number: H01L29/7869 ,  H01L21/28291 ,  H01L27/11585 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969

Abstract: An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.

公开(公告)号：US20140343880A1

公开(公告)日：2014-11-20

申请号：US13894021

申请日：2013-05-14

Applicant: United Microelectronics Corp.

Inventor： Yi-Ting Wu ,  Cheng-Tung Huang ,  Tsung-Han Lee ,  Yi-Han Ye

IPC: G06F17/11 ,  G01R19/00

CPC classification number: G01R19/0084 ,  G01R31/2621

Abstract: A method for deriving characteristic values of a MOS transistor is described. A set of ηk values is provided. A set of VBi values (i=1 to M, M≧3) is provided. A set of RSDi,j (i=1 to M−1, j=i+1 to M) values each under a pair of VBi and VBj, or a set of Vtq—q,j (q is one of 1 to M, j is 1 to M excluding q) values under VBq is derived for each ηk, with an iteration method. The ηk value making the set of RSDi,j values or Vtq—q,j values closest to each other is determined as an accurate ηk value. The mean value of RSDi,j at the accurate ηk value is calculated as an accurate RSD value.

Abstract translation: 描述用于导出MOS晶体管的特性值的方法。 提供了一组＆eegr k值。 提供一组VBi值（i = 1〜M，M≥3）。 一组RSDi，j（i = 1〜M-1，j = i + 1〜M）的值分别为一对VBi和VBj，或一组Vtq-q，j（q为1〜M ，j为1到M，不包括q）使用迭代方法为每个＆eegr k导出VBq下的值。 使得最接近的RSDi，j值或Vtq-q，j值的集合被确定为精确的k值。 RSDi，j在精确的k值的平均值被计算为准确的RSD值。