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41.发明公开公开(公告)号：US20240172456A1
公开(公告)日：2024-05-23
申请号：US18420684
申请日：2024-01-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Kai Hsu , Hui-Lin Wang , Ching-Hua Hsu , Yi-Yu Lin , Ju-Chun Fan , Hung-Yueh Chen
CPC classification number: H10B63/80 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N70/063 , H10N70/24 , H10N70/826 , H10N70/8833
Abstract: A method of manufacturing a hybrid random access memory in a system-on-chip, including steps of providing a semiconductor substrate with a magnetoresistive random access memory (MRAM) region and a resistive random-access memory (ReRAM) region, forming multiple ReRAM cells in the ReRAM region on the semiconductor substrate, forming a first dielectric layer on the semiconductor substrate, wherein the ReRAM cells are in the first dielectric layer, forming multiple MRAM cells in the MRAM region on the first dielectric layer, and forming a second dielectric layer on the first dielectric layer, wherein the MRAM cells are in the second dielectric layer.
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公开(公告)号：US20240130246A1
公开(公告)日：2024-04-18
申请号：US18395646
申请日：2023-12-25
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Ju-Chun Fan , Ching-Hua Hsu , Yi-Yu Lin , Hung-Yueh Chen
Abstract: A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric (IMD) layer on a substrate and a metal interconnection in the first IMD layer, forming a magnetic tunneling junction (MTJ) and a top electrode on the metal interconnection, forming a spacer adjacent to the MTJ and the top electrode, forming a second IMD layer around the spacer, forming a cap layer on the top electrode, the spacer, and the second IMD layer, and then patterning the cap layer to form a protective cap on the top electrode and the spacer.
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43.发明授权公开(公告)号：US11925035B2
公开(公告)日：2024-03-05
申请号：US17973557
申请日：2022-10-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Kai Hsu , Hui-Lin Wang , Ching-Hua Hsu , Yi-Yu Lin , Ju-Chun Fan , Hung-Yueh Chen
CPC classification number: H10B63/80 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N70/063 , H10N70/24 , H10N70/826 , H10N70/8833
Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
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公开(公告)号：US20230263067A1
公开(公告)日：2023-08-17
申请号：US18135758
申请日：2023-04-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to the MTJ and extended to overlap a top surface of the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is adjacent to the top electrode and the MTJ and on the second IMD layer and a top surface of the cap layer is higher than a top surface of the first IMD layer.
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公开(公告)号：US11700775B2
公开(公告)日：2023-07-11
申请号：US17090859
申请日：2020-11-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Ju-Chun Fan , Yi-Yu Lin , Ching-Hua Hsu , Hung-Yueh Chen
Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.
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Patent Agency Ranking
公开(公告)号：US20230200257A1
公开(公告)日：2023-06-22
申请号：US18110337
申请日：2023-02-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Chen-Yi Weng , Jing-Yin Jhang , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.
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公开(公告)号：US20230101233A1
公开(公告)日：2023-03-30
申请号：US18074533
申请日：2022-12-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.
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48.发明申请公开(公告)号：US20230050435A1
公开(公告)日：2023-02-16
申请号：US17973557
申请日：2022-10-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Kai Hsu , Hui-Lin Wang , Ching-Hua Hsu , Yi-Yu Lin , Ju-Chun Fan , Hung-Yueh Chen
Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.
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公开(公告)号：US11552241B2
公开(公告)日：2023-01-10
申请号：US15930425
申请日：2020-05-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Po-Kai Hsu , Hung-Yueh Chen , Yu-Ping Wang
Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first metal interconnection on a substrate; forming a stop layer on the first metal interconnection; removing the stop layer to form a first opening; forming an electromigration enhancing layer in the first opening; and forming a second metal interconnection on the electromigration enhancing layer. Preferably, top surfaces of the electromigration enhancing layer and the stop layer are coplanar.
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公开(公告)号：US20220199897A1
公开(公告)日：2022-06-23
申请号：US17692203
申请日：2022-03-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hung-Chan Lin , Yu-Ping Wang , Hung-Yueh Chen
Abstract: A magnetoresistive random access memory, including a substrate, a conductive plug in the substrate, wherein the conductive plug has a notched portion on one side of the upper edge of the conductive plug, and a magnetic memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction on the bottom electrode and a top electrode on the magnetic tunnel junction, wherein the bottom surface of the magnetic memory cell and the top surface of the conductive plug completely align and overlap each other.
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