公开(公告)号：US11749748B2

公开(公告)日：2023-09-05

申请号：US17367647

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/66462

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US11610973B2

公开(公告)日：2023-03-21

申请号：US17564104

申请日：2021-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/49 ,  H01L29/66

Abstract: A high voltage transistor structure includes a substrate. A metal gate is disposed on the substrate. At least one insulating material structure penetrates the metal gate. A metal compound layer is disposed between the metal gate and the substrate, between the insulating material structure and the substrate. The metal compound layer is a continuous structure. A gate dielectric layer is disposed under the metal compound layer and contacts the substrate.

公开(公告)号：US20210336044A1

公开(公告)日：2021-10-28

申请号：US17367647

申请日：2021-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Wei-Jen Chen

IPC: H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L21/308 ,  H01L29/66

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; removing the hard mask to form a first recess for exposing the barrier layer; removing the hard mask adjacent to the first recess to form a second recess; and forming a p-type semiconductor layer in the first recess and the second recess.

公开(公告)号：US11011430B2

公开(公告)日：2021-05-18

申请号：US16726201

申请日：2019-12-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L27/12 ,  H01L27/092 ,  H01L27/108 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.

公开(公告)号：US20210134981A1

公开(公告)日：2021-05-06

申请号：US16701051

申请日：2019-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Wei-Jen Chen ,  Kai-Lin Lee

IPC: H01L29/66

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

公开(公告)号：US20200006153A1

公开(公告)日：2020-01-02

申请号：US16052600

申请日：2018-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Kai-Lin Lee ,  Wei-Jen Chen

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/8238

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.

公开(公告)号：US09640661B1

公开(公告)日：2017-05-02

申请号：US15144840

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Yu-Hao Huang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7854

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a fin-shaped structure is formed on the substrate. Next, a gate structure is formed on the fin-shaped structure, and an epitaxial layer is formed adjacent to the gate structure. Preferably, the epitaxial layer includes a V-shaped profile viewing from the top. According to the preferred embodiment of the present invention, the V-shaped profile of the epitaxial layer allows more stress to be applied to the region having concentrated currents or edges of the fin-shaped structures during an on-state, and at the same time prevent exerting too much stress to the region having high currents or central region of the fin-shaped structure during an off-state.