公开(公告)号：US09640661B1

公开(公告)日：2017-05-02

申请号：US15144840

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Lin Lee ,  Zhi-Cheng Lee ,  Yu-Hao Huang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/31111 ,  H01L21/31116 ,  H01L29/0649 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7854

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a fin-shaped structure is formed on the substrate. Next, a gate structure is formed on the fin-shaped structure, and an epitaxial layer is formed adjacent to the gate structure. Preferably, the epitaxial layer includes a V-shaped profile viewing from the top. According to the preferred embodiment of the present invention, the V-shaped profile of the epitaxial layer allows more stress to be applied to the region having concentrated currents or edges of the fin-shaped structures during an on-state, and at the same time prevent exerting too much stress to the region having high currents or central region of the fin-shaped structure during an off-state.

公开(公告)号：US10014406B2

公开(公告)日：2018-07-03

申请号：US15238696

申请日：2016-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Yu-Hao Huang ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.

公开(公告)号：US20180012992A1

公开(公告)日：2018-01-11

申请号：US15238696

申请日：2016-08-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhi-Cheng Lee ,  Yu-Hao Huang ,  Kai-Lin Lee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device and a forming method thereof, the semiconductor device includes a first and a second wells, a source region, a drain region, two gate structures and at least one doping region. The first well with a first conductive type is disposed in a substrate, and the source region is disposed in the first well. The second well with a second conductive type is disposed adjacent to the first well in a substrate, and the drain region is disposed in the second well. Two gate structures are disposed on the substrate between the source region and the drain region. At least one doping region with the first conductive type is disposed in the second well between the two gate structures.