公开(公告)号：US5613075A

公开(公告)日：1997-03-18

申请号：US585598

申请日：1996-01-12

申请人： Nicholas Wade ,  Mark Lalich ,  Bruce Young

发明人： Nicholas Wade ,  Mark Lalich ,  Bruce Young

IPC分类号： G06F13/16 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/1673 ,  G06F13/4027

摘要： A method for guaranteeing access to a bus master for reads of main memory in a bridge circuit for joining a host processor, main memory, and a PCI bus, by detecting a read with data posted in the posted write buffer, disabling the posted write buffer, disabling access by the host processor for a selected period, detecting the presence of a retry of the read access, and enabling the posted write buffer after detecting an idle bus for the passage of the preselected time.

摘要翻译： 一种用于通过检测利用发布在写入缓冲器中的数据进行读取来保证访问总线主机以访问用于连接主处理器，主存储器和PCI总线的桥接电路中的主存储器的方法，禁用发布的写入缓冲器 ，禁止所述主机处理器访问所选择的周期，检测所述读取访问的重试的存在，以及在检测到空闲总线以通过所述预选时间之后启用所述发布的写入缓冲器。

公开(公告)号：US5572718A

公开(公告)日：1996-11-05

申请号：US259472

申请日：1994-06-14

申请人： Mike Scriber ,  Bruce Young

发明人： Mike Scriber ,  Bruce Young

IPC分类号： G06F1/10 ,  G06F1/04

CPC分类号： G06F1/10

摘要： A computer includes a mother board having a clock A thereon that provides a primary clock to a clock distribution buffer that distributes the clock that drives it to clock electronic components on the mother board. The mother board has a socket for receiving an optional module having a clock B thereon. A clock switching circuit is connected to the clock A and to the clock B socket terminus. An edge detector connected to clock B detects an edge of the clock B. A detection window indicator is asserted upon a predetermined condition, such as that power is on and stable. A control circuit, connected to the clock switching circuit, to the edge detector and to the detection window indicator causes the secondary clock to be selected and substituted for the primary clock.

摘要翻译： 计算机包括其上具有时钟A的母板，其将时钟分配缓冲器提供主时钟，时钟分配缓冲器将驱动它的时钟分配给母板上的时钟电子部件。 母板具有用于接收其上具有时钟B的可选模块的插座。 时钟切换电路连接到时钟A和时钟B插座终端。 连接到时钟B的边缘检测器检测时钟B的边缘。检测窗口指示器在预定条件下被断言，例如电源接通并稳定。 连接到时钟切换电路的控制电路连接到边缘检测器和检测窗口指示器，使得选择辅助时钟并代替主时钟。

公开(公告)号：US5954821A

公开(公告)日：1999-09-21

申请号：US929624

申请日：1997-09-15

申请人： Bruce Young

发明人： Bruce Young

IPC分类号： G06F13/36 ,  G06F1/10 ,  G06F9/445 ,  G06F13/40 ,  G06F13/42 ,  G06F1/04

CPC分类号： G06F13/4045 ,  G06F1/10

摘要： An apparatus and method for providing PCI slot expansion. An asynchronous PCI to PCI bridge for insertion into a host PCI slot is coupled via a cabled PCI bus to an expansion module. The bridge establishes two distinct time domains. An expansion clock signal is generated and its timing matched for consistent arrival throughout the expansion clock domain. An expanded number of PCI slots are thereby available to the host system.

摘要翻译： 一种用于提供PCI插槽扩展的装置和方法。 用于插入主机PCI插槽的异步PCI到PCI桥接器经由有线PCI总线耦合到扩展模块。 桥梁建立了两个不同的时间域。 产生扩展时钟信号，并且其时序与整个扩展时钟域内的一致到达相匹配。 因此，扩展数量的PCI插槽可用于主机系统。

公开(公告)号：US5761458A

公开(公告)日：1998-06-02

申请号：US850643

申请日：1997-05-02

申请人： Bruce Young ,  Rick Coulson

发明人： Bruce Young ,  Rick Coulson

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4027

摘要： An intelligent bus bridge contained in a single integrated circuit chip along with computer systems and server systems that employ intelligent input/output subsystems. The intelligent bus bridge includes a local processor coupled for communication over a local component bus, a local memory controller that enables access to a local memory from the local component bus, and a component bus bridge that propagates accesses between the local component bus and a system component bus. The single integrated circuit chip enables dual-porting of the local memory controller without significant increases in input/output pins. A mode control input to the intelligent bus bridge indicates whether the intelligent bus bridge functions in a local master mode or a host master mode in a computer or server system.

摘要翻译： 包含在单个集成电路芯片中的智能总线桥以及采用智能输入/输出子系统的计算机系统和服务器系统。 智能总线桥包括本地处理器，其耦合用于通过本地组件总线进行通信，本地存储器控制器能够从本地组件总线访问本地存储器，以及传播本地组件总线和系统之间的访问的组件总线桥 组件总线 单个集成电路芯片可实现本地存储器控制器的双端口，而不会显着增加输入/输出引脚。 智能总线桥的模式控制输入指示智能总线桥是在计算机或服务器系统中的本地主机模式还是主机主机模式下工作。

公开(公告)号：US5717873A

公开(公告)日：1998-02-10

申请号：US734730

申请日：1996-10-21

申请人： Jeffrey L. Rabe ,  Nicholas D. Wade ,  Bruce Young

发明人： Jeffrey L. Rabe ,  Nicholas D. Wade ,  Bruce Young

IPC分类号： G06F13/40 ,  G06F13/28

CPC分类号： G06F13/4036

摘要： Apparatus and a method for eliminating deadlock in a multibus computer system which system includes a primary bus, and a secondary bus, a bridge circuit for joining the primary bus to a bus master, and a second bridge circuit for joining the primary bus to the secondary bus. The invention causes the second bridge circuit to generate a first signal directed to the all bridge circuits to indicate that a bus master on the secondary bus desires access to the secondary bus. All bridge circuits holding data directed to a component on the secondary bus flushes all temporary storage means holding data directed to a component on the secondary bus. The bridge circuits then generate signals to indicate that flushing is complete and the bus master on the secondary bus is granted access to the secondary bus. In one embodiment, the second bridge tests to determine whether the bus master requesting access requires a guaranteed access time and generates a signal to flush temporary storage in the first bridge between memory and the bridge.

摘要翻译： 一种用于消除多总线计算机系统中的死锁的装置和方法，该系统包括主总线和辅助总线，用于将主总线连接到总线主机的桥接电路和用于将主总线连接到次级总线的第二桥接电路 总线。 本发明使得第二桥接电路产生指向全桥电路的第一信号，以指示辅助总线上的总线主机需要访问辅助总线。 保持指向辅助总线上的组件的数据的所有桥接电路刷新所有临时存储装置，其保持指向次级总线上的组件的数据。 然后，桥接电路产生信号以指示冲洗完成，并且次级总线上的总线主机被授予对辅助总线的访问。 在一个实施例中，第二桥接器测试以确定请求访问的总线主机是否需要保证访问时间，并且生成用于冲洗存储器和桥接器之间的第一桥中的临时存储器的信号。

公开(公告)号：US5630094A

公开(公告)日：1997-05-13

申请号：US375972

申请日：1995-01-20

申请人： George Hayek ,  Ali S. Oztaskin ,  Brian Langendorf ,  Bruce Young

发明人： George Hayek ,  Ali S. Oztaskin ,  Brian Langendorf ,  Bruce Young

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/40 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F12/0835 ,  G06F13/1684 ,  G06F13/4059

摘要： A computer system having an integrated bus bridge and memory controller circuit and method for enabling access to a shared memory with high bandwidth data streaming are disclosed. The integrated bus bridge and memory controller circuit performs a series of snoop ahead transactions over a first bus during access transactions to the shared memory that originate over a second bus and thereby enables high bandwidth data streaming on the second bus. The integrated bus bridge and memory controller circuit includes a peripheral write buffer that buffers write data received over the second bus and that stores a snoop done flag for the write data that indicates whether a corresponding snoop ahead transaction for the write data is complete. The integrated bus bridge and memory controller circuit further includes a peripheral read prefetch buffer that prefetches read data during read transactions over the second bus only after a corresponding snoop ahead transaction for the read data is complete.

摘要翻译： 公开了具有集成总线桥和存储器控制器电路和方法的计算机系统，该电路和方法能够访问具有高带宽数据流的共享存储器。 集成总线桥接器和存储器控制器电路在通过第二总线发起到共享存储器的访问事务期间通过第一总线执行一系列前置提前事务，从而实现第二总线上的高带宽数据流传输。 集成总线桥接器和存储器控制器电路包括外围写入缓冲器，其缓冲通过第二总线接收的写入数据，并且存储用于写入数据的窥探完成标志，该数据指示用于写入数据的对应的窥探事件是否完成。 集成总线桥接器和存储器控制器电路还包括一个外设读取预取缓冲器，只有在读取数据的相应窥探事件完成之后，才能通过第二总线在读取事务期间预取读取数据。

公开(公告)号：US20110039434A1

公开(公告)日：2011-02-17

申请号：US12541440

申请日：2009-08-14

申请人： Luis Sosa ,  Robert Hobbs ,  Bruce Young

发明人： Luis Sosa ,  Robert Hobbs ,  Bruce Young

IPC分类号： H01R4/60 ,  H01R43/20

CPC分类号： H01R4/188 ,  Y10T29/49208

摘要： An improved full tension connector for electrical conductors has a substantially cylindrical outer surface and a stepped series of substantially cylindrical inner surfaces with progressively smaller inside diameters. The design of the connector allows for improved control of the compression of the cable inside the fitting. A series of swages, progressing successively from a light compression to a heavier compression, ensures that the connector will sustain the required tensile load.

摘要翻译： 用于电导体的改进的全张力连接器具有基本上圆柱形的外表面和具有逐渐更小的内径的基本上圆柱形的内表面的阶梯系列。 连接器的设计允许改进对配件内的电缆的压缩的控制。 从轻压缩到较重的压缩，连续进行的一系列措施确保连接器能够承受所需的拉伸载荷。

公开(公告)号：US20070234394A1

公开(公告)日：2007-10-04

申请号：US11278035

申请日：2006-03-30

申请人： Richard Skeie ,  Bruce Young

发明人： Richard Skeie ,  Bruce Young

IPC分类号： H04N7/173

CPC分类号： H04B1/0035

摘要： The present invention utilizes station preset buttons on a radio frequency receiver to allow the user to browse through the various subchannels included in a single station or channel. The preset buttons still have the standard function of having a frequency and subchannel selection parameter associated with the button that can be used to directly select that subchannel. But subsequent presses of the button may change the currently playing program to a different program contained in the same station or channel using a circular queue ordering.

摘要翻译： 本发明利用射频接收机上的台站预设按钮，允许用户浏览包括在单个站或频道中的各个子信道。 预置按钮仍然具有标准功能，其具有与该按钮相关联的频率和子通道选择参数，该参数可用于直接选择该子通道。 但是随后按下按钮可以使用循环队列排序将当前播放的节目改变为包含在同一台或频道中的不同节目。

公开(公告)号：US20060114246A1

公开(公告)日：2006-06-01

申请号：US10988151

申请日：2004-11-12

申请人： Bruce Young

发明人： Bruce Young

IPC分类号： G09G5/00

CPC分类号： H04N21/4858 ,  G09G2340/0407 ,  G09G2340/0442 ,  G09G2340/125 ,  G09G2360/02 ,  G09G2370/04 ,  H04N5/44504 ,  H04N7/0122 ,  H04N21/42221 ,  H04N21/4312 ,  H04N21/4314

摘要： The present invention is directed to a method and apparatus for storing an aspect ratio setting for each of multiple inputs of a display device, so that, when displaying content from each input, the aspect ratio setting of the display device is set to the value for the aspect ratio setting stored for that input. Furthermore, the aspect ratio setting for each input may be preset and may be changed by the user with the help of an on screen display.

摘要翻译： 本发明涉及一种用于存储显示装置的多个输入中的每一个的宽高比设置的方法和装置，使得当从每个输入显示内容时，将显示装置的宽高比设置设置为 存储该输入的宽高比设置。 此外，每个输入的宽高比设置可以是预设的，并且可以借助于屏幕显示由用户改变。

公开(公告)号：US06862636B2

公开(公告)日：2005-03-01

申请号：US09992438

申请日：2001-11-16

申请人： Bruce Young

发明人： Bruce Young

IPC分类号： H04R3/00 ,  G06F13/00 ,  H04B1/18 ,  H04R25/00

CPC分类号： H04R3/00 ,  H04R2420/01

摘要： A speaker system that detects what type of audio signal is supplied to it and automatically adjusts to reproduce sound from either an analog audio input signal or a digital audio input signal. The speaker system has one or more converters to convert each form of digital audio into analog audio, a detection means to detect whether an analog audio input signal or one of the possible digital audio signals is present and a multiplexer to switch between either the analog audio input signal or one of the outputs of the digital audio converters. Amplifier and speaker drivers are shown for completeness.

摘要翻译： 扬声器系统，其检测提供给哪种类型的音频信号，并自动调整以从模拟音频输入信号或数字音频输入信号中再现声音。 扬声器系统具有一个或多个转换器，用于将每种形式的数字音频转换成模拟音频，检测装置用于检测模拟音频输入信号或可能的数字音频信号中的一个是否存在以及复用器在模拟音频之间切换 输入信号或数字音频转换器的输出之一。 显示放大器和扬声器驱动程序的完整性。