公开(公告)号：US3997896A

公开(公告)日：1976-12-14

申请号：US591965

申请日：1975-06-30

申请人： Frank V. Cassarino, Jr. ,  George J. Bekampis ,  John W. Conway ,  Richard A. Lemay

发明人： Frank V. Cassarino, Jr. ,  George J. Bekampis ,  John W. Conway ,  Richard A. Lemay

IPC分类号： G06F11/14 ,  G06F13/18 ,  G06F13/378 ,  G06F13/42 ,  G06F13/00

CPC分类号： G06F11/1497 ,  G06F13/18 ,  G06F13/378 ,  G06F13/4213

摘要： In a data processing system which includes a common bus to which a plurality of units are connected for the transfer of information, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a split bus cycle operation in which the master unit requesting information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a later slave generated bus transfer cycle. Means are provided for enabling any other units to communicate over the common bus during the time between the first cycle and such later cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively in an interleaved manner.

摘要翻译： 在包括连接多个单元以用于信息传送的公共总线的数据处理系统中，在异步生成的总线传送周期期间，信息可以由最高优先级请求单元传送。 逻辑被提供用于实现分割总线周期操作，其中主单元在第一总线传送周期期间从从单元请求信息可以在随后从站产生的总线传输周期期间从从单元接收这种信息。 提供了用于使得任何其他单元能够在从单元响应的第一周期与后期周期之间的时间期间通过公共总线进行通信，从而使得至少两对单元能够以交错方式彼此通信 。

公开(公告)号：US5291580A

公开(公告)日：1994-03-01

申请号：US771703

申请日：1991-10-04

申请人： Raymond D. Bowden, III ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Jeffrey S. Somers

发明人： Raymond D. Bowden, III ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Jeffrey S. Somers

IPC分类号： G06F13/42 ,  G06F13/28

CPC分类号： G06F13/4243

摘要： A memory system tightly couples to a high performance microprocessor through a synchronous bus. The logic circuits included in the memory system generate a blipper pulse signal using successive transitions of clock pulse signals other than the edges used to synchronize microprocessor and memory operations. The blipper pulse signal is logically combined with the memory's column address strobe timing signal which is derived from the synchronizing edges of clock pulse signals which defines the duration of the column address interval required for accessing of a pair of DRAM memories during successive memory cycles for providing sequences of four memory read responses with no wait state.

摘要翻译： 存储器系统通过同步总线紧密耦合到高性能微处理器。 包括在存储器系统中的逻辑电路使用不同于用于同步微处理器和存储器操作的边缘的时钟脉冲信号的连续转换来产生blipper脉冲信号。 blipper脉冲信号与存储器的列地址选通定时信号进行逻辑结合，该定时信号是从时钟脉冲信号的同步边沿导出的，该时钟脉冲信号定义在连续存储器周期期间访问一对DRAM存储器所需的列地址间隔的持续时间，以提供 四个内存读取响应的序列，无等待状态。

公开(公告)号：US5274825A

公开(公告)日：1993-12-28

申请号：US969551

申请日：1992-10-30

申请人： Richard A. Lemay ,  Michael D. Smith

发明人： Richard A. Lemay ,  Michael D. Smith

IPC分类号： G06F13/26 ,  G06F13/00

CPC分类号： G06F13/26

摘要： A data processing system includes a number of subsystems coupled in common to a system bus. The subsystems communicate with each other by sending commands to each other via the system bus. Channel numbers identify the subsystems. One subsystem includes apparatus for receiving commands requiring a priority interrupt by storing vectors in a random access memory. These vectors which are addressed by the channel number of the interrupting subsystem indicate the offset to be added to the base address of an exception vector table. The exception vector stores the starting address in a memory of the requested interrupt routine.

摘要翻译： 数据处理系统包括多个子系统共同耦合到系统总线。 子系统通过系统总线相互发送命令相互通信。 频道号标识子系统。 一个子系统包括通过将向量存储在随机存取存储器中来接收需要优先中断的命令的装置。 由中断子系统的通道号寻址的这些向量指示要添加到异常向量表的基地址的偏移量。 异常向量将开始地址存储在请求的中断程序的存储器中。

公开(公告)号：US4809276A

公开(公告)日：1989-02-28

申请号：US19908

申请日：1987-02-27

申请人： Richard A. Lemay ,  David A. Wallace

发明人： Richard A. Lemay ,  David A. Wallace

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F11/22

CPC分类号： G06F11/1024 ,  G06F11/076 ,  G06F11/22 ,  G06F2201/88

摘要： Memory failure detection apparatus is disclosed which is used with a large capacity memory that is organized in banks of memory, and with which error correction circuitry is used to correct correctable errors and provide an indication of same. The detection apparatus is responsive to the error indications and to a bank select addressing signal to provide and store error counts for a bank or banks of memory located on each memory board. A system processor periodically reads the error counts and responds to same to provide a maintenance message indicating that a specific memory board is to be replaced.

摘要翻译： 本发明公开了一种存储器故障检测装置，其与存储器组中的大容量存储器一起使用，并且利用哪个纠错电路来校正可校正的错误并提供相同的指示。 检测装置响应于错误指示和存储体选择寻址信号，以提供并存储位于每个存储器板上的存储体或存储体的错误计数。 系统处理器周期性地读取错误计数并对其进行响应以提供指示要更换特定存储器板的维护消息。