公开(公告)号：US4872110A

公开(公告)日：1989-10-03

申请号：US92863

申请日：1987-09-03

申请人： Michael D. Smith ,  Richard A. Lemay

发明人： Michael D. Smith ,  Richard A. Lemay

IPC分类号： G06F13/12

CPC分类号： G06F13/126

摘要： A data processing system includes a number of subsystems all coupled in common to a system bus and communicate with each other by sending and receiving commands sent over the system bus. A central processing subsystem includes a response memory for storing indication of the responses sent by the receiving subsystem when receiving commands sent by the central processing subsystem. The responses include an acknowledge response, a not acknowledge response or no response--a timeout. Storing the acknowledge response and the timeout will enable the programmer to determine which of the three responses was received.

公开(公告)号：US4727486A

公开(公告)日：1988-02-23

申请号：US858786

申请日：1986-05-02

申请人： Michael D. Smith ,  Llewelyn S. Dunwell ,  Richard A. Lemay ,  Robert C. Miller ,  Theodore R. Staplin, Jr. ,  William E. Woods ,  John L. Curley

发明人： Michael D. Smith ,  Llewelyn S. Dunwell ,  Richard A. Lemay ,  Robert C. Miller ,  Theodore R. Staplin, Jr. ,  William E. Woods ,  John L. Curley

IPC分类号： G06F12/10 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30

CPC分类号： G06F12/1054

摘要： A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

公开(公告)号：US5274825A

公开(公告)日：1993-12-28

申请号：US969551

申请日：1992-10-30

申请人： Richard A. Lemay ,  Michael D. Smith

发明人： Richard A. Lemay ,  Michael D. Smith

IPC分类号： G06F13/26 ,  G06F13/00

CPC分类号： G06F13/26

摘要： A data processing system includes a number of subsystems coupled in common to a system bus. The subsystems communicate with each other by sending commands to each other via the system bus. Channel numbers identify the subsystems. One subsystem includes apparatus for receiving commands requiring a priority interrupt by storing vectors in a random access memory. These vectors which are addressed by the channel number of the interrupting subsystem indicate the offset to be added to the base address of an exception vector table. The exception vector stores the starting address in a memory of the requested interrupt routine.

摘要翻译： 数据处理系统包括多个子系统共同耦合到系统总线。 子系统通过系统总线相互发送命令相互通信。 频道号标识子系统。 一个子系统包括通过将向量存储在随机存取存储器中来接收需要优先中断的命令的装置。 由中断子系统的通道号寻址的这些向量指示要添加到异常向量表的基地址的偏移量。 异常向量将开始地址存储在请求的中断程序的存储器中。

公开(公告)号：US5983012A

公开(公告)日：1999-11-09

申请号：US128456

申请日：1993-09-28

申请人： Richard S. Bianchi ,  Dennis R. Flynn ,  Marcia T. Fogelgren ,  Richard A. Lemay ,  Mary E. Tovell ,  William E. Woods

发明人： Richard S. Bianchi ,  Dennis R. Flynn ,  Marcia T. Fogelgren ,  Richard A. Lemay ,  Mary E. Tovell ,  William E. Woods

IPC分类号： G06F1/00 ,  G06F9/455 ,  G06F9/46 ,  G06F13/10 ,  G06F21/00

CPC分类号： G06F21/31 ,  G06F13/10 ,  G06F13/105 ,  G06F21/6281 ,  G06F9/45537 ,  G06F2221/2105

摘要： An emulator executes on a second data processing system as a second system user level process including a first system user level program, a first system executive program, and first system user and executive tasks. An emulator level is interposed between the second system user level process and a kernel level and contains pseudo device drivers. Each pseudo device driver corresponds to a first system input/output device. The kernel level includes kernel processes, each kernel process corresponding to a pseudo device driver. The second system hardware platform includes a plurality of second system input/output devices, wherein each second system input output device corresponds to a kernel process. Each combination of a pseudo device driver, a corresponding kernel process and a corresponding second system input/output device executes in a second system process and emulates the operations of a corresponding first system input/output task and the corresponding first system input/output device. The pseudo device drivers are constructed of a plurality of pseudo device queues, a return queue and a queue manager.

摘要翻译： 模拟器在第二数据处理系统上执行，作为包括第一系统用户级程序，第一系统执行程序以及第一系统用户和执行任务的第二系统用户级进程。 在第二系统用户级别进程和内核级别之间插入一个仿真器级别，并包含伪设备驱动程序。 每个伪设备驱动程序对应于第一系统输入/输出设备。 内核级别包括内核进程，每个内核进程对应一个伪设备驱动程序。 第二系统硬件平台包括多个第二系统输入/输出设备，其中每个第二系统输入输出设备对应于内核进程。 伪设备驱动器，相应的内核进程和对应的第二系统输入/输出设备的每个组合在第二系统进程中执行并且模拟对应的第一系统输入/输出任务和对应的第一系统输入/输出设备的操作。 伪设备驱动程序由多个伪设备队列，返回队列和队列管理器构成。

公开(公告)号：US5446847A

公开(公告)日：1995-08-29

申请号：US531

申请日：1993-01-04

申请人： James W. Keeley ,  George J. Barlow ,  Richard A. Lemay

发明人： James W. Keeley ,  George J. Barlow ,  Richard A. Lemay

IPC分类号： G06F13/372 ,  G06F13/18

CPC分类号： G06F13/372

摘要： A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.

摘要翻译： 总线接口优先级网络通过多个不同类型的请求者提供对系统总线的访问，作为它们需要处理的事务的类型的函数。 该网络包括用于识别请求者的类型的可编程电路，并且基于请求者类型选择访问系统总线的延迟，从而消除了对最慢请求者调整定时的需要。

公开(公告)号：US5341495A

公开(公告)日：1994-08-23

申请号：US771297

申请日：1991-10-04

申请人： Thomas F. Joyce ,  James W. Keeley ,  Richard A. Lemay ,  Bruno DiPlacido, Jr. ,  Martin M. Massucci

发明人： Thomas F. Joyce ,  James W. Keeley ,  Richard A. Lemay ,  Bruno DiPlacido, Jr. ,  Martin M. Massucci

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/4027

摘要： A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.

摘要翻译： 处理单元紧密地耦合到利用分离循环总线协议的系统总线，并且包括可以从这种总线访问的本地存储器。 本地存储器耦合到根据预定总线协议操作的高速同步总线。 处理单元包括耦合到高速同步总线和异步系统总线的状态机。 状态机在从使用分离周期协议的系统总线传送发给本地存储器的命令时模拟预定的总线同步协议。

公开(公告)号：US5136500A

公开(公告)日：1992-08-04

申请号：US366225

申请日：1989-06-12

申请人： Richard A. Lemay ,  Kenneth J. Izbicki ,  David A. Wallace ,  William E. Woods

发明人： Richard A. Lemay ,  Kenneth J. Izbicki ,  David A. Wallace ,  William E. Woods

IPC分类号： G06F13/16 ,  G06F15/167

CPC分类号： G06F15/167 ,  G06F13/1663

摘要： A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.

公开(公告)号：US4935737A

公开(公告)日：1990-06-19

申请号：US927632

申请日：1986-11-05

申请人： Kenneth J. Izbicki ,  William E. Woods ,  Richard A. Lemay

发明人： Kenneth J. Izbicki ,  William E. Woods ,  Richard A. Lemay

IPC分类号： G06F7/76

CPC分类号： G06F7/76

摘要： A data selection matrix is disclosed which uses a plurality of programmed array logic (PAL) units having input thereto portions of binary words from a plurality of sources, the PALs being responsive to control words also input thereto to jointly select one of said sources of binary words and to select the arrangement of the portions of the binary words being input thereto from the selected source of binary words.

摘要翻译： 公开了一种数据选择矩阵，其使用多个编程的阵列逻辑（PAL）单元，其具有从多个源输入二进制字的部分，PAL响应于也输入到其的控制字来共同选择所述二进制源之一 并且从所选择的二进制字源中选择从其输入的二进制字的部分的排列。

公开(公告)号：US4775929A

公开(公告)日：1988-10-04

申请号：US917940

申请日：1986-10-14

申请人： Kenneth J. Izbicki ,  William E. Woods ,  Richard A. Lemay ,  Steven A. Taque

发明人： Kenneth J. Izbicki ,  William E. Woods ,  Richard A. Lemay ,  Steven A. Taque

IPC分类号： G06F13/42 ,  G06F13/00

CPC分类号： G06F13/4217

摘要： What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement. Some of the processor circuits have a control lead input that is energized by the clock signal output from the system clock so that they accept information from one bus to which their input is connected during a first polarity portion of a clock cycle and return either unprocessed or processed information to another bus during a second polarity portion of a clock cycle.

摘要翻译： 所公开的是用于计算机系统中的时间分配总线布置，其中其中不同的电路通过多个总线互连，并且操作使得可以从一个电路中读出要处理的信息，以某种方式在另一个电路中进行处理 并且处理的信息在计算机系统中的系统时钟的一个周期内被存储在相同或另一个电路中，并且不需要连接到总线的电路中的总线控制电路和总线接口。 一些电路的输入/输出仅连接到总线中的单个总线，而其他电路的输入连接到一个总线，其输出连接到不同的总线，而其他电路的输入或输出连接到 总线中的一个和其他输入/输出连接到总线布置外部的电路。 一些处理器电路具有由从系统时钟输出的时钟信号激励的控制引线输入，使得它们在时钟周期的第一极性部分期间接收来自其输入连接到的一个总线的信息，并返回未处理的或 在时钟周期的第二极性部分处理信息到另一个总线。

公开(公告)号：US4460959A

公开(公告)日：1984-07-17

申请号：US302904

申请日：1981-09-16

申请人： Richard A. Lemay ,  Philip E. Stanley ,  William E. Woods ,  David E. Cushing

发明人： Richard A. Lemay ,  Philip E. Stanley ,  William E. Woods ,  David E. Cushing

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0859

摘要： A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.

摘要翻译： 公开了一种由高速缓冲存储器系统和传送控制逻辑单元组成的逻辑控制系统，用于将来自中央存储器系统的程序信息和CPU（中央处理单元）指令的流程从公共通信总线上的CPU接收到CPU。 CPU和传输控制逻辑单元通过具有公共通信总线的高速缓冲存储器系统进行通信。 响应于对中央存储器系统的CPU请求，传输控制逻辑单元从高速缓冲存储器系统请求程序信息和指令，并以这样的方式呈现给CPU，以避免由信息传输延迟引起的CPU活动中断 。