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45 条记录 (耗时 0.021 秒)

    Memory controller with interleaved queuing apparatus
    3.
    发明授权
    Memory controller with interleaved queuing apparatus 失效
    具有交错排队装置的存储控制器

    公开(公告)号：US4451880A

    公开(公告)日：1984-05-29

    申请号：US202821

    申请日：1980-10-31

    申请人： Robert B. Johnson ,  Chester M. Nibby, Jr.

    发明人： Robert B. Johnson ,  Chester M. Nibby, Jr.

    IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F13/28 ,  H04L25/49 ,  G06F13/00

    CPC分类号： G06F13/1642 ,  G06F13/28

    摘要： A memory controller controls the operation of a number of memory module units and includes a number of queues which couple to the module units. Each queue includes an address queue register, a control queue register and a data queue register. Each address queue register has tristate control for independent operation. Control circuits which couple to the queue address, control and data registers assign memory cycles between queues on an alternate basis when the queue control registers store requests which are being processed. This enables the interleaving of memory requests which eliminates processing delays particularly in cases where such requests involve multiword transfers over successive memory cycles of operation.

    摘要翻译： 存储器控制器控制多个存储器模块单元的操作，并且包括耦合到模块单元的多个队列。 每个队列包括地址队列寄存器，控制队列寄存器和数据队列寄存器。 每个地址队列寄存器都有三态控制，用于独立操作。 当队列控制寄存器存储正在处理的请求时，耦合到队列地址，控制和数据寄存器的控制电路在备用的队列之间分配存储器周期。 这使得能够消除处理延迟的存储器请求的交织，特别是在这种请求涉及在连续存储器操作周期中的多字传输的情况下。

    Sequential word aligned address apparatus
    4.
    发明授权
    Sequential word aligned address apparatus 失效
    顺序字对齐地址设备

    公开(公告)号：US4376972A

    公开(公告)日：1983-03-15

    申请号：US110521

    申请日：1980-01-08

    申请人： Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Dana W. Moore

    发明人： Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Dana W. Moore

    IPC分类号： G11C11/401 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06 ,  G06F13/12 ,  G06F13/00

    CPC分类号： G06F12/04 ,  G06F12/02

    摘要： A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tri-state operated address register circuits and timing circuits. The address circuits include a pair of tri-state operated address registers which couple to the bus and to the set of address lines to each memory unit. In response to a memory request, the registers store row and column address portions of a chip address of the memory request. A multibit adder circuit is connected to increment by one the low order row address when the least significant address bits of the memory request indicate a subboundary address condition thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits upon detecting the condition cause the timing circuits to generate only timing signals necessary for accessing the first word location.

    摘要翻译： 耦合到多字总线以用于处理从其接收的存储器请求的存储器子系统包括至少一对独立可寻址的动态存储器模块单元。 每个存储器单元包括多行随机存取存储器（RAM）芯片。 子系统还包括加法器电路，一对三态操作地址寄存器电路和定时电路。 地址电路包括一对三态操作地址寄存器，其耦合到总线和到每个存储器单元的地址线集合。 响应于存储器请求，寄存器存储存储器请求的芯片地址的行和列地址部分。 当存储器请求的最低有效地址位指示子边界地址条件从而使得能够访问一对顺序字位置时，多位加法器电路被连接以递增一个低位行地址。 每当存储器请求指定不能访问双字的地址时，边界电路在检测到条件时，使定时电路仅产生访问第一字位置所必需的定时信号。

    Error detection and correction locator circuits
    5.
    发明授权
    Error detection and correction locator circuits 失效
    误差检测和校正定位电路

    公开(公告)号：US4077565A

    公开(公告)日：1978-03-07

    申请号：US727820

    申请日：1976-09-29

    申请人： Chester M. Nibby, Jr. ,  George J. Barlow

    发明人： Chester M. Nibby, Jr. ,  George J. Barlow

    IPC分类号： G06F11/10 ,  H03M13/19 ,  G11C29/00 ,  G06F11/12

    CPC分类号： G06F11/1048 ,  H03M13/19

    摘要： A main memory system includes encoder and decoder circuits. The encoder circuits are connected to receive data bits and parity bits and from them generate check code bits which are stored with the data bits during a write cycle of operation. The decoder circuits are connected to receive data and check bits read out from memory during a read cycle of operation. The decoder circuits include a plurality of decoder circuits and error locator circuits. Circuits via exclusive OR circuits generate a number of syndrome bit signals. These signals are divided into first and second groups. The first group is coded to specify which one of a number of decoder circuits comprising the error locator circuits is to be enabled in the case of an error condition. The second group of signals is coded to designate the particular data bit to be corrected by the decoder circuits. Predetermined output terminals of each of the decoder circuits representative of valid single bit data error conditions are applied to a plurality of correction circuits for modification of the data signals as specified by the decoder circuits. Additionally, signals from predetermined output terminals of certain ones of the decoder circuits representative of certain single check code bit error conditions are utilized for providing the correct parity for the data signals associated therewith.

    摘要翻译： 主存储器系统包括编码器和解码器电路。 编码器电路被连接以接收数据位和奇偶校验位，并且从它们产生在操作的写周期期间与数据位一起存储的校验码位。 在操作的读取周期期间，解码器电路被连接以接收从存储器读出的数据和校验位。 解码器电路包括多个解码器电路和误差定位器电路。 通过异或电路的电路产生多个校正子位信号。 这些信号被分成第一组和第二组。 第一组被编码以指定在错误状况的情况下启用包括错误定位器电路的多个解码器电路中的哪一个。 第二组信号被编码以指定由解码器电路校正的特定数据位。 代表有效的单位数据错误条件的每个解码器电路的预定输出端子被施加到由解码器电路指定的用于修改数据信号的多个校正电路。 此外，代表某些单个校验码位错误条件的某些解码器电路的来自预定输出端的信号被用于为与其相关联的数据信号提供正确的奇偶校验。

    Apparatus and method for storing parity encoded data from a plurality of input/output sources
    6.
    发明授权
    Apparatus and method for storing parity encoded data from a plurality of input/output sources 失效
    用于存储来自多个输入/输出源的奇偶校验编码数据的装置和方法

    公开(公告)号：US4072853A

    公开(公告)日：1978-02-07

    申请号：US727821

    申请日：1976-09-29

    申请人： George J. Barlow ,  Chester M. Nibby, Jr.

    发明人： George J. Barlow ,  Chester M. Nibby, Jr.

    IPC分类号： G06F11/10 ,  G11C29/00 ,  G06F11/12

    CPC分类号： G06F11/1024 ,  G06F11/1056

    摘要： Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check code bits read out from an addressed location are operative to generate a number of syndrome bits having a predetermined characteristic for indicating the existence of an uncorrectable error condition when the parity bits associated with data signals when written originally into memory if checked would have indicated that the data was in error.

    摘要翻译： 数据处理系统的主存储器中包括装置和方法，该数据处理系统从连接到公共总线的多个输入/输出装置接收数据。 在操作的写周期期间，设备将多个数据字节信号与相关联的奇偶校验位一起应用以写入存储器的寻址存储位置。 连接错误检测和校正编码器电路以接收数据位和奇偶校验位，并且从它们产生编码的校验码位，以根据来自给定源的奇偶校验位选择性地存在不可校正的错误状况。 在操作的读取周期期间，响应于从寻址位置读出的数据和校验码位连接到存储器的错误检测和校正解码器电路可操作以产生具有预定特性的多个校正子位，用于指示存在 当与最初写入存储器的数据信号相关联的奇偶校验位如果被检查时，将会出现数据错误的情况，这是一个不可校正的错误状态。

    High performance burst read data transfer operation
    9.
    发明授权
    High performance burst read data transfer operation 失效
    高性能突发读取数据传输操作

    公开(公告)号：US5291580A

    公开(公告)日：1994-03-01

    申请号：US771703

    申请日：1991-10-04

    申请人： Raymond D. Bowden, III ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Jeffrey S. Somers

    发明人： Raymond D. Bowden, III ,  Richard A. Lemay ,  Chester M. Nibby, Jr. ,  Jeffrey S. Somers

    IPC分类号： G06F13/42 ,  G06F13/28

    CPC分类号： G06F13/4243

    摘要： A memory system tightly couples to a high performance microprocessor through a synchronous bus. The logic circuits included in the memory system generate a blipper pulse signal using successive transitions of clock pulse signals other than the edges used to synchronize microprocessor and memory operations. The blipper pulse signal is logically combined with the memory's column address strobe timing signal which is derived from the synchronizing edges of clock pulse signals which defines the duration of the column address interval required for accessing of a pair of DRAM memories during successive memory cycles for providing sequences of four memory read responses with no wait state.

    摘要翻译： 存储器系统通过同步总线紧密耦合到高性能微处理器。 包括在存储器系统中的逻辑电路使用不同于用于同步微处理器和存储器操作的边缘的时钟脉冲信号的连续转换来产生blipper脉冲信号。 blipper脉冲信号与存储器的列地址选通定时信号进行逻辑结合，该定时信号是从时钟脉冲信号的同步边沿导出的，该时钟脉冲信号定义在连续存储器周期期间访问一对DRAM存储器所需的列地址间隔的持续时间，以提供 四个内存读取响应的序列，无等待状态。

    Memory identification apparatus and method
    10.
    发明授权
    Memory identification apparatus and method 失效
    存储器识别装置和方法

    公开(公告)号：US4545010A

    公开(公告)日：1985-10-01

    申请号：US480964

    申请日：1983-03-31

    申请人： Edward R. Salas ,  Edwin P. Fisher ,  Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Daniel A. Boudreau

    发明人： Edward R. Salas ,  Edwin P. Fisher ,  Robert B. Johnson ,  Chester M. Nibby, Jr. ,  Daniel A. Boudreau

    IPC分类号： G06F12/06 ,  G06F13/00

    CPC分类号： G06F12/0653

    摘要： A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board's memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address. In response to signals generated by the identification sections of the installed memory boards, the decoder circuits are selectively enabled to decode those bit combinations of the address portion specified by the sections for enabling successive addressing of all of the blocks of location within the system.

    摘要翻译： 存储器系统包括至少一个或多个存储器模块板，其结构相同，以及包含用于控制存储器操作的控制电路的单个计算机板。 每个板插入主板，并且包括具有多行存储器芯片的存储器部分和用于产生指示板密度的信号的电路的识别部分和用于构建电路板存储部分的存储器部件的类型的识别部分。 主板控制电路包括耦合到每个存储器模块板的识别和存储器部分的多个解码器电路。 解码器电路接收每个存储器请求地址的预定多位地址部分的不同地址位组合。 响应于由所安装的存储器板的识别部分产生的信号，解码器电路被选择性地能够解码由这些部分指定的地址部分的那些比特组合，以便能够对系统内的所有位置块进行连续寻址。