公开(公告)号：US07493503B2

公开(公告)日：2009-02-17

申请号：US11315837

申请日：2005-12-22

申请人： Alfredo Aldereguia ,  Brian E. Bigelow ,  Dhruv M. Desai ,  Scott N. Dunham ,  Nickolas J. Gruendler ,  William G. Holland ,  James E. Hughes ,  Randolph S. Kolvick ,  Challis L. Purrington ,  Michael L. Scollard ,  Gary R. Shippy

发明人： Alfredo Aldereguia ,  Brian E. Bigelow ,  Dhruv M. Desai ,  Scott N. Dunham ,  Nickolas J. Gruendler ,  William G. Holland ,  James E. Hughes ,  Randolph S. Kolvick ,  Challis L. Purrington ,  Michael L. Scollard ,  Gary R. Shippy

IPC分类号： G06F1/26

CPC分类号： G06F1/3209

摘要： A method and system are disclosed to enable and control power reduction in a blade/chassis system. A “maximum power reduction” attribute is stored in the VPD of the blade (or can otherwise be input to or retrieved or calculated by the management entity). The management module of the chassis in which the blades and power supplies are located uses this information to manage the power reduction of blades when the system is operating in an over-subscription mode and a power supply fails. If throttling is required, the system knows the amount of power reduction available for each blade and controls the throttling by spreading it out among the blades in the system so that, ideally, no blade will cease operation altogether.

摘要翻译： 公开了一种方法和系统，以实现和控制刀片/底盘系统中的功率降低。 “最大功率降低”属性存储在刀片的VPD中（否则可以由管理实体输入或检索或计算）。 其中叶片和电源所在的机箱的管理模块使用该信息来管理当系统以超订购模式操作并且电源出现故障时叶片的功率降低。 如果需要节流，则系统知道每个刀片可用的功率减少量，并通过将系统中的刀片扩展到控制器中来控制节流，从而理想地，刀片不会完全停止运行。

公开(公告)号：US07492723B2

公开(公告)日：2009-02-17

申请号：US11176922

申请日：2005-07-07

申请人： William T. Boyd ,  Douglas M. Freimuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

发明人： William T. Boyd ,  Douglas M. Freimuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

IPC分类号： H04L12/50

CPC分类号： G06F13/4045

摘要： A mechanism, method and computer usable medium is provided for each root node of a multiple root node system and its own independent address space. This mechanism also allows multiple system images within the same root node to have their own independent address spaces. A mechanism is also provided for incorporating legacy root node and input/output adapters that are non-aware of the mechanisms introduced by this invention. Input/ output adapters which implement this invention may also have the number of functions that they support greatly expanded beyond the present eight functions per input/output adapter.

摘要翻译： 为多根节点系统的每个根节点及其自己的独立地址空间提供了一种机制，方法和计算机可用介质。 该机制还允许同一根节点内的多个系统映像具有自己的独立地址空间。 还提供了一种机制，用于结合不知道本发明引入的机制的传统根节点和输入/输出适配器。 实现本发明的输入/输出适配器还可以具有超过每个输入/输出适配器的当前八个功能大大扩展的功能数量。

公开(公告)号：US07474623B2

公开(公告)日：2009-01-06

申请号：US11260619

申请日：2005-10-27

申请人： William T. Boyd ,  Douglas M. Freimuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

发明人： William T. Boyd ,  Douglas M. Freimuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

IPC分类号： H04B7/212

CPC分类号： G06F11/0775 ,  G06F11/0712 ,  G06F11/0724 ,  G06F11/0784

摘要： A method and apparatus is provided for routing error messages in a distributed computer system comprising multiple root nodes, and further comprising one or more PCI switches and one or more I/O adapters, wherein each root node includes one or more system images. In one useful embodiment, a method is provided for routing I/O error messages to root nodes respectively associated with the errors contained in the messages. The method includes detecting occurrence of an error at a specified one of the adapters, wherein the error affects one of the system images, and generating an error message at the specified adapter. The method further comprises routing the error message from the specified adapter to the particular root node that includes the affected system image. The error message is then selectively processed at the particular root node, in order to identify the affected system image. Usefully, the step of routing the error message includes using a bus/device/function number associated with the error, together with a routing table located in one of the PCI switches, to route the error message to the correct root node and system image.

摘要翻译： 提供了一种用于在包括多个根节点的分布式计算机系统中路由错误消息的方法和装置，并且还包括一个或多个PCI交换机和一个或多个I / O适配器，其中每个根节点包括一个或多个系统映像。 在一个有用的实施例中，提供了一种用于将I / O错误消息路由到分别与消息中包含的错误相关联的根节点的方法。 该方法包括检测指定的一个适配器中的错误的发生，其中该错误影响系统映像之一，并在指定的适配器处生成错误消息。 该方法还包括将错误消息从指定的适配器路由到包括受影响的系统映像的特定根节点。 然后在特定根节点处选择性地处理错误消息，以便识别受影响的系统映像。 有用的是，路由错误消息的步骤包括使用与错误相关联的总线/设备/功能号码以及位于其中一个PCI交换机中的路由表将错误消息路由到正确的根节点和系统映像。

公开(公告)号：US20080235431A1

公开(公告)日：2008-09-25

申请号：US12136009

申请日：2008-06-09

申请人： William T. Boyd ,  Douglas M. Freimuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

发明人： William T. Boyd ,  Douglas M. Freimuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

IPC分类号： G06F13/00

CPC分类号： G06F13/4022

摘要： A method is directed to use of a master root node, in a distributed computer system provided with multiple root nodes, to control the configuration of routings through an I/O switched-fabric. One of the root nodes is designated as the master root node or PCI Configuration Manager (PCM), and is operable to carry out the configuration while each of the other root nodes remains in a quiescent or inactive state. In one useful embodiment pertaining to a system of the above type, that includes multiple root nodes, PCI switches, and PCI adapters available for sharing by different root nodes, a method is provided wherein the master root node is operated to configure routings through the PCI switches. Respective routings are configured between respective root nodes and the PCI adapters, wherein each of the configured routings corresponds to only one of the root nodes. A particular root node is enabled to access each of the PCI adapters that are included in any configured routing that corresponds to the particular root node. At the same time, the master root node writes into a particular root node only the configured routings that correspond to the particular root node. Thus, the particular root node is prevented from accessing an adapter that is not included in its corresponding routings.

摘要翻译： 一种方法涉及在具有多个根节点的分布式计算机系统中使用主根节点来控制通过I / O交换结构的路由的配置。 一个根节点被指定为主根节点或PCI配置管理器（PCM），并且可操作以在每个其他根节点保持处于静态或非活动状态的同时执行配置。 在与上述类型的系统相关的一个有用的实施例中，其包括可用于不同根节点共享的多个根节点，PCI交换机和PCI适配器，提供了一种方法，其中主根节点被操作以配置通过PCI的路由 开关。 相应的路由被配置在相应的根节点和PCI适配器之间，其中每个配置的路由仅对应于根节点之一。 特定根节点能够访问包含在与特定根节点对应的任何配置的路由中的每个PCI适配器。 同时，主根节点将特定根节点只写入与特定根节点对应的已配置路由。 因此，防止特定根节点访问未包括在其对应的路由中的适配器。

公开(公告)号：US20080235430A1

公开(公告)日：2008-09-25

申请号：US12134952

申请日：2008-06-06

申请人： William T. Boyd ,  Douglas M. Fremiuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

发明人： William T. Boyd ,  Douglas M. Fremiuth ,  William G. Holland ,  Steven W. Hunter ,  Renato J. Recio ,  Steven M. Thurber ,  Madeline Vega

IPC分类号： G06F3/00

CPC分类号： G06F13/4022 ,  H04L45/00 ,  H04L45/54

摘要： A method is provided for creating and managing tables for routing packets through an environment that includes multiple hosts and shared PCI switches and adapters. A Destination Identification (DID) field in the PBA is appended to a transaction packet dispatched through the PCI switches, wherein a particular DID is associated with a particular host or system image, and thus identifies the physical or virtual end point of its packet. In one embodiment, packets are routed through PCI switches in a distributed computer system comprising multiple root nodes, wherein each root node includes one or more hosts. The embodiment includes the step of creating a table or like data structure in a specified one of the switches. When a particular host of one of the root nodes becomes connected to the specified switch, a PCI Configuration Master (PCM), residing in one of the root nodes, is operated to enter a destination identifier or DID into the table. The DID is then appended as an address component, to packets directed through the specified switch from the particular host to one of the adapters. The destination identifier is also used to determine that a PCI packet, routed through the specified switch from one of the adapters, is intended for the particular root node.

摘要翻译： 提供了一种创建和管理表以通过包括多个主机和共享PCI交换机和适配器的环境路由数据包的方法。 PBA中的目的地标识（DID）字段附加到通过PCI交换机分派的事务分组，其中特定的DID与特定主机或系统映像相关联，并且因此标识其分组的物理或虚拟终点。 在一个实施例中，分组通过包括多个根节点的分布式计算机系统中的PCI交换机路由，其中​​每个根节点包括一个或多个主机。 该实施例包括在指定的一个开关中创建表或类似数据结构的步骤。 当一个根节点的特定主机连接到指定的交换机时，驻留在其中一个根节点的PCI配置主机（PCM）被操作以在表中输入目的地标识符或DID。 然后，将DID作为地址组件附加到通过指定的交换机从特定主机引导到其中一个适配器的数据包。 目的地标识符还用于确定通过指定交换机从其中一个适配器路由的PCI数据包是针对特定根节点的。

公开(公告)号：US06163820A

公开(公告)日：2000-12-19

申请号：US419552

申请日：1999-10-19

申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F13/14

CPC分类号： G06F5/065 ,  G06F3/06 ,  G06F2205/064 ,  G06F2205/066

摘要： A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

摘要翻译： 通过系统I / O总线在存储器和I / O设备中的非连续缓冲器之间传送数据的方法使用存储在存储器中的描述符队列。 每个描述符指向缓冲区并包括缓冲区的长度。 I / O设备提供队列的基地址，队列的长度以及初始化时的基址与基地址相同的当前地址。 当要传送数据时，位于处理器中的设备驱动程序将可用描述符（DescrEnq）的数量发送到单独或以突发模式访问描述符的I / O设备，以访问由描述符标识的数据缓冲区。

公开(公告)号：US6049842A

公开(公告)日：2000-04-11

申请号：US847034

申请日：1997-05-01

申请人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

发明人： Henry Michael Garrett ,  William G. Holland ,  Joseph Franklin Logan ,  Joseph Gerald McDonald ,  John Kenneth Stacy

IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F13/14

CPC分类号： G06F5/065 ,  G06F3/06 ,  G06F2205/064 ,  G06F2205/066

摘要： A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

公开(公告)号：US5608876A

公开(公告)日：1997-03-04

申请号：US447022

申请日：1995-05-22

申请人： Ariel Cohen ,  William G. Holland ,  Joseph F. Logan ,  Avi Parash

发明人： Ariel Cohen ,  William G. Holland ,  Joseph F. Logan ,  Avi Parash

IPC分类号： G06F13/36 ,  G06F12/06 ,  G06F13/14 ,  G06F13/00

CPC分类号： G06F12/0684

摘要： An adapter or add-in card for use in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded. Another circuit arrangement presents the Expansion ROM base address register as a `read/write` register or a read only register with all bits set to logical "0 " to the PCI computer. If the Expansion ROM base address register is presented as a read only register with all bits set to "0 ", the PCI computer concludes that no Expansion ROM exists on the add-in card, and its contents are not shadowed into the memory of the PCI computer. This disabling of the Expansion ROM causes memory space to be conserved in the computer. If the Expansion ROM is presented as a read/write register with non-zero values, the PCI computer concludes that an Expansion ROM exists and "shadows" its contents into the memory of the PCI computer.

摘要翻译： 用于外围组件互连（PCI）计算机的适配器或附加卡包括将卡耦合到PCI总线的通用模块。 该模块包括一组选择性可编程配置寄存器，它们由适配器上的微处理器加载。 模块上的电路布置发出一个命令，禁止PCI处理器访问配置寄存器，直到完全加载。 另一个电路装置将扩展ROM基地址寄存器作为“读/写”寄存器或只读寄存器，将所有位设置为逻辑“0”给PCI计算机。 如果扩展ROM基地址寄存器被显示为所有位设置为“0”的只读寄存器，则PCI计算机得出结论，附加卡中不存在扩展ROM，并且其内容不会被遮蔽到存储器中 PCI电脑。 这种禁用扩展ROM会使存储空间在计算机中保存。 如果扩展ROM作为非零值的读/写寄存器显示，则PCI计算机得出结论，扩展ROM存在，并将其内容“阴影”到PCI计算机的存储器中。