公开(公告)号：US20110254121A1

公开(公告)日：2011-10-20

申请号：US12761780

申请日：2010-04-16

申请人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： H01L23/525 ,  H01L21/768 ,  G06F17/50

CPC分类号： H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

摘要翻译： 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

公开(公告)号：US08471356B2

公开(公告)日：2013-06-25

申请号：US12761780

申请日：2010-04-16

申请人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/525

CPC分类号： H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

摘要翻译： 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。

公开(公告)号：US20090280636A1

公开(公告)日：2009-11-12

申请号：US12118161

申请日：2008-05-09

申请人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76849 ,  H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

摘要翻译： 提供了用于制造包含用于电熔丝和其它相关应用的各种封盖材料的互连结构的方法。 该方法包括形成具有第一界面结构并形成与第一结构相邻的第二互连结构的第一互连结构。 第二互连结构形成有与第一互连结构的第一界面结构不同的第二界面结构。

公开(公告)号：US08772156B2

公开(公告)日：2014-07-08

申请号：US12118161

申请日：2008-05-09

申请人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76849 ,  H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure.

摘要翻译： 提供了用于制造包含用于电熔丝和其它相关应用的各种封盖材料的互连结构的方法。 该方法包括形成具有第一界面结构并形成与第一结构相邻的第二互连结构的第一互连结构。 第二互连结构形成有与第一互连结构的第一界面结构不同的第二界面结构。

公开(公告)号：US08558384B2

公开(公告)日：2013-10-15

申请号：US13537879

申请日：2012-06-29

申请人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5256 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

摘要翻译： 为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。 该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。 第二互连结构具有与第一界面结构不同的第二界面结构。

公开(公告)号：US08471296B2

公开(公告)日：2013-06-25

申请号：US13011215

申请日：2011-01-21

申请人： Kangguo Cheng ,  Louis C. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Kangguo Cheng ,  Louis C. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： H01L23/52 ,  H01L21/326

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to the planar surface of the substrate). The tops are positioned at distal ends of the fins relative to the substrate. An insulating layer covers the tops and the sidewalls of the fins and covers an intervening substrate portion of the planar surface of the substrate located between the fins. A metal layer covers the insulating layer. A pair of conductive contacts are connected to the metal layer at locations where the metal layer is adjacent the top of the fins.

摘要翻译： 一种方法形成eFuse结构，其具有从衬底的平面（垂直于平面的方向）突出的一对相邻半导体翅片。 散热片具有平面侧壁（垂直于基板的平面）和平面顶部（平行于基板的平面）。 顶部相对于基底定位在翅片的远端。 绝缘层覆盖翅片的顶部和侧壁，并且覆盖位于翅片之间的衬底的平面表面的中间衬底部分。 金属层覆盖绝缘层。 在金属层邻近翅片顶部的位置处，一对导电触头连接到金属层。

公开(公告)号：US07956466B2

公开(公告)日：2011-06-07

申请号：US12118186

申请日：2008-05-09

申请人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/73 ,  H01L29/74

CPC分类号： H01L23/5256 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

摘要翻译： 为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。 该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。 第二互连结构具有与第一界面结构不同的第二界面结构。

公开(公告)号：US20090278228A1

公开(公告)日：2009-11-12

申请号：US12118186

申请日：2008-05-09

申请人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76849 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure.

摘要翻译： 为包含用于电熔丝和其它相关应用的各种封盖材料的互连结构提供了一种设计结构。 该结构包括具有第一界面结构的第一互连结构和与第一结构相邻的第二互连结构。 第二互连结构具有与第一界面结构不同的第二界面结构。

公开(公告)号：US09620619B2

公开(公告)日：2017-04-11

申请号：US13348894

申请日：2012-01-12

申请人： Veeraraghavan S. Basker ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Veeraraghavan S. Basker ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/20 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/78

摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

公开(公告)号：US09059254B2

公开(公告)日：2015-06-16

申请号：US13604660

申请日：2012-09-06

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。