公开(公告)号：US20060087344A1

公开(公告)日：2006-04-27

申请号：US10974660

申请日：2004-10-27

申请人： Gregory Snider ,  Philip Kuekes

发明人： Gregory Snider ,  Philip Kuekes

IPC分类号： H03K19/00

CPC分类号： B82Y10/00 ,  G11C13/02 ,  G11C2213/77 ,  G11C2213/81 ,  H03K19/02 ,  Y10S977/789

摘要： Various embodiments of the present invention are directed to implementation and use of logic-state-storing, impedance-encoded nanoscale, impedance-encoded latches that store logic values as impedance states within nanoscale electronic circuits that employ impedance-driven logic. In certain of these embodiments, use of nanoscale, impedance-encoded latches together with nanoscale electronic circuits that employ impedance-driven logic avoids cumulative degradation of voltage margins along a cascaded series of logic circuits and provides for temporary storage of intermediate logic values, allowing for practical interconnection of nanowire-crossbar-implemented logic circuits through nanoscale, impedance-encoded latches to other nanowire-crossbar-implemented logic circuits in order to implement complex, nanoscale-logic-circuit pipelines, nanoscale-logic-circuit-based state machines, and other complex logic devices with various different interconnection topologies and corresponding functionalities.

摘要翻译： 本发明的各种实施例涉及逻辑状态存储，阻抗编码的纳米级阻抗编码锁存器，其将逻辑值存储为采用阻抗驱动逻辑的纳米级电子电路内的阻抗状态。 在这些实施例的某些实施例中，使用纳米级阻抗编码的锁存器以及采用阻抗驱动逻辑的纳米级电子电路避免了沿着级联的一系列逻辑电路的电压裕度的累积劣化，并提供临时存储中间逻辑值，允许 将纳米线交叉开关逻辑电路通过纳米尺度阻抗编码的锁存器实际互连到其他纳米线交叉开关逻辑电路，以便实现复杂的纳米级逻辑电路管线，基于纳米级逻辑电路的状态机和 具有各种不同互连拓扑和相应功能的其他复杂逻辑器件。

公开(公告)号：US20050055387A1

公开(公告)日：2005-03-10

申请号：US10659892

申请日：2003-09-10

申请人： Philip Kuekes ,  Gadiel Seroussi ,  Richard Williams

发明人： Philip Kuekes ,  Gadiel Seroussi ,  Richard Williams

IPC分类号： G06F11/10 ,  G11C8/10 ,  G11C8/20 ,  G11C13/00 ,  G06J1/00

CPC分类号： G06F11/1016 ,  B82Y10/00 ,  G11C8/10 ,  G11C13/0014 ,  G11C2213/77 ,  G11C2213/81

摘要： Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the signal-level classes, and defect-and-fault tolerant systems embodying the methods. An electronic-device embodiment including an array of nanowire crossbars, the nanoscale memory elements within the nanowire crossbars addressed through conventional microelectronic address lines, and a method embodiment for providing fault-tolerant interconnection interfaces with electrically distinguishable signal levels are described. In the described embodiment, in order to interconnect microelectronic address lines with the nanowire crossbars within the electronic memory, an address encoding technique is employed to generate a number of redundant, parity-check address lines to supplement a minimally required set of address signal lines needed to access the nanoscale memory elements.

摘要翻译： 用于增加包含相互连接的部件的系统中的缺陷容忍度和容错性的方法，其中根据分离信号级别类别的一个或多个阈值将信号级别分类为多个不同的可区分类别之一，以及缺陷和 体现这种方法的容错系统。 描述了一种电子器件实施例，其包括纳米线交叉杆阵列，通过常规微电子地址线寻址的纳米线交叉管内的纳米级存储元件，以及用于提供具有电可区分信号电平的容错互连接口的方法实施例。 在所描述的实施例中，为了将微电子地址线与电子存储器内的纳米线交叉点互连，采用地址编码技术来生成多个冗余的奇偶校验地址线，以补充所需的最低要求的地址信号线组 以访问纳米尺度的存储元件。