Abstract:
Examples of the present disclosure generally relate to integrated circuits, such as a system-on-chip (SoC), that include a memory subsystem. In some examples, an integrated circuit includes a first master circuit in a first power domain on a chip; a second master circuit in a second power domain on the chip; and a first memory controller in a third power domain on the chip. The first master circuit and the second master circuit each are configured to access memory via the first memory controller. The first power domain and the second power domain each are separate and independent from the third power domain.
Abstract:
Visualizing operations of a memory controller includes reading, using a processor, a plurality of commands of a memory controller from a data store, wherein the commands are associated with times of issue. Blocks are displayed for the plurality of commands upon a display device as a raster image. The blocks are ordered according to the times of issue of the commands represented by the blocks. The blocks are visually distinguished according to command type within the raster image.
Abstract:
In an example, a programmable integrated circuit (IC) includes programmable logic, a processing system, and a network controller. The network controller includes a media access control unit (MAC), a first interface to a physical transceiver, a second interface to the processing system, and a third interface between the MAC and the programmable logic.
Abstract:
In an example, a programmable integrated circuit (IC) includes programmable logic and a display controller. The display controller includes a first interface coupled to receive coded data, a renderer to generate display-agnostic data from the coded data, a transmitter to generate display data from the display-agnostic data in accordance with a first protocol, a second interface coupled to provide the display data as output, and a third interface coupled to provide the display-agnostic data to the programmable logic.