公开(公告)号：US4539490A

公开(公告)日：1985-09-03

申请号：US494266

申请日：1985-05-13

申请人： Shoji Ariizumi ,  Makoto Segawa

发明人： Shoji Ariizumi ,  Makoto Segawa

IPC分类号： G05F3/20 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/02 ,  H01L27/04 ,  G11C11/40

CPC分类号： G11C11/4074 ,  G05F3/205 ,  G11C5/146 ,  H01L27/0222

摘要： The region constituting the rectify-charge pump circuit of a self substrate bias circuit is surrounded by a capacitive region, and the fluctuated minority carriers induced in this region are absorbed.

摘要翻译： 构成自衬底偏置电路的整流电荷泵电路的区域由电容区域包围，并且在该区域中感应到的波动的少数载流子被吸收。

公开(公告)号：US4504746A

公开(公告)日：1985-03-12

申请号：US365897

申请日：1982-04-06

申请人： Makoto Segawa ,  Shoji Ariizumi

发明人： Makoto Segawa ,  Shoji Ariizumi

IPC分类号： G11C11/413 ,  G11C8/06 ,  G11C11/41 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H03K17/687 ,  H03K19/096 ,  G11C8/00

CPC分类号： G11C8/06

摘要： An address buffer circuit is provided which has first and second MOS transistors whose current paths are connected in series with each other and whose gates are supplied with input signals of opposite phases, and third and fourth MOS transistors whose current paths are connected in series with each other. The first and third MOS transistors are of I-type. The gate of the third MOS transistor is connected to a junction of the first and second MOS transistors and the gates of the second and fourth MOS transistors are commonly connected. The address buffer circuit further has a MOS transistor which controls the conduction state of the third MOS transistor in response to an external control signal.

摘要翻译： 提供了一种地址缓冲器电路，其具有第一和第二MOS晶体管，其电流路径彼此串联连接，并且其栅极被提供有相反相位的输入信号;以及第三和第四MOS晶体管，其电流路径与每个MOS晶体管串联连接 其他。 第一和第三MOS晶体管是I型。 第三MOS晶体管的栅极连接到第一和第二MOS晶体管的结，并且第二和第四MOS晶体管的栅极共同连接。 地址缓冲电路还具有MOS晶体管，其响应于外部控制信号来控制第三MOS晶体管的导通状态。