公开(公告)号：US4399520A

公开(公告)日：1983-08-16

申请号：US235859

申请日：1981-02-19

申请人： Shoji Ariizumi ,  Makoto Segawa ,  Hisaaki Maiwa ,  Seishi Okamoto

发明人： Shoji Ariizumi ,  Makoto Segawa ,  Hisaaki Maiwa ,  Seishi Okamoto

IPC分类号： G11C11/403 ,  G11C11/412 ,  G11C19/18 ,  H01L27/105 ,  G11C7/00

CPC分类号： H01L27/105 ,  G11C11/403 ,  G11C11/412 ,  G11C19/18

摘要： A semiconductor integrated circuit having a memory and an adjacent peripheral circuit generating minority carriers which can destroy data in a portion of the memory at low temperatures. The load resistance in the portion is made lower or the storage capacity is made higher in the portion than in the remainder of the memory so that at low temperatures data is not lost and the energy consumption of the circuit is not unduly increased.

摘要翻译： 具有存储器和相邻外围电路的半导体集成电路产生少量载流子，这些载流子可以在低温下破坏存储器的一部分中的数据。 部分中的负载电阻降低或存储容量在存储器的剩余部分中比存储容量高，使得在低温下数据不会丢失，并且电路的能量消耗不会不适当地增加。

公开(公告)号：US4384220A

公开(公告)日：1983-05-17

申请号：US229746

申请日：1981-01-29

申请人： Makoto Segawa ,  Shoji Ariizumi

发明人： Makoto Segawa ,  Shoji Ariizumi

IPC分类号： G11C11/41 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  H01L29/78 ,  H03K19/00 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/096 ,  H03K17/687 ,  H03K19/094 ,  H03K19/20

CPC分类号： H03K19/09445 ,  H03K19/0016 ,  H03K19/01855 ,  H03K19/096

摘要： An MOS transistor circuit contains at least one "zero" threshold mode transistor to provide a power-down function for the circuit. The "zero" threshold mode transistor is connected between an enhancement-mode MOS driver transistor and a depletion-mode MOS load transistor.

摘要翻译： MOS晶体管电路包含至少一个“零”阈值模式晶体管，为电路提供掉电功能。 “零”阈值模式晶体管连接在增强型MOS驱动晶体管和耗尽型MOS负载晶体管之间。

公开(公告)号：US4578694A

公开(公告)日：1986-03-25

申请号：US429183

申请日：1982-09-30

申请人： Shoji Ariizumi ,  Makoto Segawa

发明人： Shoji Ariizumi ,  Makoto Segawa

IPC分类号： H03K19/0944 ,  H01L27/02 ,  H01L27/088 ,  H02H9/04 ,  H03K19/003 ,  H01L27/04 ,  H01L29/78 ,  H03K17/08 ,  H03K17/687

CPC分类号： H01L27/0883 ,  H01L27/0251 ,  H03K19/00315 ,  H01L2924/0002 ,  H02H9/046

摘要： An integrated circuit serving as an E/D type inverter circuit and provided with a gate-protection circuit. The inverter circuit is constructed of an E type MOSFET having a gate coupled to an input signal and a D type MOSFET which operates as load, and the gate-protective circuit is constructed by a MOSFET which is connected between a power supply and the D type MOSFET and whose gate is connected to the power supply. The gate of the D type MOSFET is protected by the gate-protection circuit even if noise exists on the power supply line.

摘要翻译： 作为E / D型逆变器电路的集成电路，具有栅极保护电路。 逆变器电路由具有耦合到输入信号的栅极的E型MOSFET和作为负载工作的D型MOSFET构成，栅极保护电路由连接在电源和D型之间的MOSFET构成 MOSFET，其栅极连接到电源。 即使电源线上存在噪声，D型MOSFET的栅极也受到栅极保护电路的保护。

公开(公告)号：US4554469A

公开(公告)日：1985-11-19

申请号：US469631

申请日：1983-02-25

申请人： Makoto Segawa ,  Shoji Ariizumi

发明人： Makoto Segawa ,  Shoji Ariizumi

IPC分类号： G11C11/413 ,  G11C8/10 ,  G11C8/18 ,  G11C11/418 ,  H03K5/02 ,  H03K17/06 ,  H03K19/094

CPC分类号： G11C11/418 ,  G11C8/10 ,  G11C8/18

摘要： A semiconductor circuit has a static bootstrap circuit, which includes a first MOS transistor with an input signal supplied to the gate and having the current path connected between a voltage source terminal and a node, a second MOS transistor having the gate connected to receive an inverted form of the input signal after a delay time and having the current path connected between the node and a reference potential terminal and a capacitor connected between the gate of the first MOS transistor and the node. The semiconductor circuit also has a short pulse generator. The bootstrap circuit further includes a third MOS transistor having the current path connected between the output terminal of the short pulse generator and the node and with the input signal supplied to the gate and fourth and fifth MOS transistors having the respective gates connected to the gates of the first and second MOS transistors and the respective current paths connected in series between the voltage source terminal and reference potential terminal.

摘要翻译： 半导体电路具有静态自举电路，其包括第一MOS晶体管，其具有提供给栅极的输入信号，并且具有连接在电压源端子和节点之间的电流路径;第二MOS晶体管，其栅极连接以接收反相 在延迟时间之后输入信号的形式，并且连接在节点和参考电位端之间的电流路径以及连接在第一MOS晶体管的栅极和节点之间的电容器。 半导体电路还具有短脉冲发生器。 自举电路还包括第三MOS晶体管，其具有连接在短脉冲发生器的输出端和节点之间的电流路径以及提供给栅极的输入信号，以及连接到栅极的第四和第五MOS晶体管， 第一和第二MOS晶体管和各个电流路径串联连接在电压源端子和参考电位端子之间。

公开(公告)号：US4541006A

公开(公告)日：1985-09-10

申请号：US571948

申请日：1984-01-19

申请人： Shoji Ariizumi ,  Makoto Segawa

发明人： Shoji Ariizumi ,  Makoto Segawa

IPC分类号： G11C11/412 ,  G11C11/418 ,  H01L21/02 ,  H01L21/764 ,  H01L21/822 ,  H01L21/8244 ,  H01L23/528 ,  H01L27/04 ,  H01L27/06 ,  H01L27/11 ,  G11C11/40

CPC分类号： H01L28/20 ,  G11C11/412 ,  G11C11/418 ,  H01L21/764 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1112 ,  H01L2924/0002

摘要： A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above the drain of the first insulation gate FET transistor, and the second polycrystalline silicon layer is provided above the drain of the second insulation gate FET transistor.

摘要翻译： 一种具有半导体衬底的半导体器件，其中形成有与作为第一和第二反相器的负载的第一和第二多晶硅层串联连接的第一和第二绝缘栅FET晶体管晶体管。 第一多晶硅层设置在第一绝缘栅FET晶体管的漏极之上，第二多晶硅层设置在第二绝缘栅FET晶体管的漏极之上。

公开(公告)号：US4760560A

公开(公告)日：1988-07-26

申请号：US900517

申请日：1986-08-26

申请人： Shoji Ariizumi ,  Makoto Segawa ,  Shigeto Mizukami

发明人： Shoji Ariizumi ,  Makoto Segawa ,  Shigeto Mizukami

IPC分类号： G05F3/20 ,  G11C5/14 ,  H01L27/02 ,  H01L27/105 ,  G11C7/00 ,  G11C11/34 ,  H01L27/10 ,  H01L27/15

CPC分类号： G05F3/205 ,  G11C5/146 ,  H01L27/0218 ,  H01L27/105

摘要： A random access memory comprises a semiconductor body of one conductivity type, at least one first well region of an opposite conductivity type formed in the surface area of the semiconductor body, and a memory cell array having a plurality of memory cells formed in the first well region. A peripheral circuit for driving the memory cell array is formed in at least one second well region of the opposite conductivity type formed separately from the first well region in the surface area of the semiconductor body. The second well region is set at a bias level deeper than the first well region.

摘要翻译： 随机存取存储器包括一个导电类型的半导体本体，形成在该半导体本体的表面区域中的至少一个相反导电类型的第一阱区，以及一个存储单元阵列，具有形成在第一阱中的多个存储单元 地区。 用于驱动存储单元阵列的外围电路形成在与半导体本体的表面区域中的第一阱区分开形成的相反导电类型的至少一个第二阱区域中。 第二阱区被设置在比第一阱区更深的偏置电平。

公开(公告)号：US4673969A

公开(公告)日：1987-06-16

申请号：US814295

申请日：1985-12-30

申请人： Shoji Ariizumi ,  Makoto Segawa

发明人： Shoji Ariizumi ,  Makoto Segawa

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11 ,  H01L23/48

CPC分类号： H01L28/20 ,  H01L21/76889 ,  H01L23/5283 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/927

摘要： A semiconductor device having a pair of wiring layers connected in parallel with each other in which a first wiring layer is formed over a semiconductor substrate through a insulation layer. The first wiring layer is made of poly-Si and has relatively high resistivity. Therefore a second wiring layer is formed over the first wiring layer through an insulation layer. A portion of the second wiring layer has low conductivity and is parallel connected to the first wiring layer in order to reduce the resistivity of the wiring layer. Another portion of the second wiring layer has low conductivity and is used as resistive means.

摘要翻译： 一种具有彼此并联连接的一对布线层的半导体器件，其中通过绝缘层在半导体衬底上形成第一布线层。 第一布线层由多晶硅制成，电阻率较高。 因此，通过绝缘层在第一布线层上形成第二布线层。 为了降低布线层的电阻率，第二布线层的一部分具有低导电性并且并联连接到第一布线层。 第二布线层的另一部分具有低导电性并且用作电阻装置。

公开(公告)号：US4648075A

公开(公告)日：1987-03-03

申请号：US669361

申请日：1984-11-08

申请人： Makoto Segawa ,  Shoji Ariizumi

发明人： Makoto Segawa ,  Shoji Ariizumi

IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C11/40

CPC分类号： G11C29/808

摘要： A redundancy circuit for a semiconductor memory device of the byte configuration type, in which data is read out for each bit, is comprised of a main memory having a plurality of main memory cells arrayed in a matrix fashion, the matrix array being divided into memory sections in the column direction; a spare memory for saving defective memory cells contained in the main memory, the spare memory comprising spare rows of a plurality of spare memory cells arranged in the row direction, the spare row being provided for each of the main memory sections; programmable spare row decoders provided for each row of spare memory cells and for independently selecting each row of the spare memory cell; and main-decoder-disable signal-generating circuits provided for each of the memory sections and for placing all of the row main decoders of the corresponding memory section in non-select state in response to a signal derived from the programmed spare row decoder of the corresponding memory section.

摘要翻译： 用于每个位读出数据的字节配置类型的半导体存储器件的冗余电路由具有以矩阵方式排列的多个主存储单元的主存储器组成，矩阵阵列被分成存储器 列方向的部分; 用于存储包含在主存储器中的有缺陷的存储器单元的备用存储器，所述备用存储器包括沿行方向布置的多个备用存储单元的备用行，为每个主存储器区域提供备用行; 为每行备用存储单元提供可编程备用行解码器，并独立地选择备用存储单元的每一行; 以及为每个存储器部分提供的主解码器禁止信号发生电路，并且用于响应于从编程的备用行解码器导出的信号将相应的存储器部分的所有行主解码器放置在非选择状态 相应的存储器部分。

公开(公告)号：US4453175A

公开(公告)日：1984-06-05

申请号：US187794

申请日：1980-09-16

申请人： Shoji Ariizumi ,  Makoto Segawa

发明人： Shoji Ariizumi ,  Makoto Segawa

IPC分类号： G11C11/412 ,  G11C11/418 ,  H01L21/02 ,  H01L21/764 ,  H01L23/528 ,  H01L27/06 ,  H01L27/11 ,  H01L27/04 ,  G11C11/40 ,  H01L29/78

CPC分类号： H01L28/20 ,  G11C11/412 ,  G11C11/418 ,  H01L21/764 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/1112 ,  H01L2924/0002

摘要： A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected, respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

摘要翻译： 一种具有半导体衬底的半导体器件，其中分别与用作第一和第二反相器的负载的第一和第二多晶硅层串联连接的第一和第二绝缘栅FET晶体管晶体管。 第一多晶硅层设置在第二绝缘栅FET晶体管的栅极上方，第二多晶硅层设置在第一绝缘栅FET晶体管的栅电极的上方。

公开(公告)号：US4725746A

公开(公告)日：1988-02-16

申请号：US421885

申请日：1982-09-23

申请人： Makoto Segawa ,  Shoji Ariizumi

发明人： Makoto Segawa ,  Shoji Ariizumi

IPC分类号： H03K19/017 ,  H03K4/24 ,  H03K ,  H03K17/06 ,  H03K17/687

CPC分类号： H03K19/01714

摘要： A semiconductor circuit has first and second MOS transistors which are connected between an output terminal and a positive and a reference power source terminal, respectively, a bootstrap capacitor connected between the output terminal and the gate of the first MOS transistor, an inverter which inverts the input signal and which supplies the inverted signal to the gate of the second MOS transistor after a predetermined delay timne, and a switching MOS transistor having a current path connected between the input terminal and the gate of the first MOS transistor. The switching MOS transistor has a threshold voltage greater than that of the second MOS transistor.

摘要翻译： 半导体电路具有分别连接在输出端和正极和基准电源端之间的第一和第二MOS晶体管，连接在第一MOS晶体管的输出端和栅极之间的自举电容器，反相器 并且在经过预定延迟时间之后将反相信号提供给第二MOS晶体管的栅极;以及开关MOS晶体管，其具有连接在第一MOS晶体管的输入端和栅极之间的电流通路。 开关MOS晶体管的阈值电压大于第二MOS晶体管的阈值电压。