公开(公告)号：US09087003B2

公开(公告)日：2015-07-21

申请号：US13666289

申请日：2012-11-01

Applicant: Leo G. Dehner ,  Oded Yishay

Inventor： Leo G. Dehner ,  Oded Yishay

IPC: G06F17/14 ,  G06F1/03

CPC classification number: G06F17/142 ,  G06F1/0328 ,  G06F17/14

Abstract: A method and apparatus may be used to generate complex exponentials for either frequency domain or time domain applications by programming input parameter values into a complex exponential vector generator (260) having a frequency generator stage (281) and a vector phase accumulator stage (282) arranged with a vector element multiplier stage (283) to generate complex exponential phase index values (α0, α1, . . . αv−1) that are processed by a complex exponential generator stage (284) to output a plurality of complex exponential values (e.g., ej2πα0, ej2πα1, . . . ej2παv−1) that may be rearranged by a permutation unit (286) for use by vector data path.

Abstract translation: 方法和装置可以用于通过将输入参数值编程到具有频率发生器级（281）和矢量相位累加器级（282）的复指数矢量生成器（260）中来为频域或时域应用产生复指数， 布置有矢量元素乘法器级（283）以产生由复指数发生器级（284）处理的复数指数相位索引值（α0，α1，...αv-1），以输出多个复指数值 例如ej2＆pgr;α0，ej2＆pgr;α1，... ej2＆pgr;αv-1），其可以由置换单元（286）重新排列以供矢量数据路径使用。

公开(公告)号：US20140222882A1

公开(公告)日：2014-08-07

申请号：US13760012

申请日：2013-02-05

Applicant: Hong Kong Applied Science & Technology Research Institute Company Limited

Inventor： Zhongzi CHEN ,  Beiping YAN ,  Xiao HUO ,  Xiaowu CAI

IPC: G06F17/10

CPC classification number: G06F1/0321 ,  G06F1/0328 ,  G06F1/0353 ,  G06F1/0356

Abstract: A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

Abstract translation: 直接数字合成器（DDS）的正弦波发生器将数字相位输入转换为数字正弦波输出。 正弦值和斜率存储在只读存储器（ROM）中用于第一象限中的粗略高位相位。 象限文件夹和分相器反映和反转第一象限的值，以产生所有四个象限的幅度。 每个正弦值和斜率都存储在较低相位位的范围内。 一个Delta位分离高位和低位相位。 Delta有条件地反转低位相位，正弦值和最终极性。 减少的AND逻辑阵列将斜率乘以有条件反相的下相位位。 然后，重建的ADD逻辑阵列会添加有条件反转的正弦值。 添加有条件反转的极性以产生最终正弦值。 基于Delta位的条件反演精简生成逻辑。

公开(公告)号：US08674777B1

公开(公告)日：2014-03-18

申请号：US13615482

申请日：2012-09-13

Applicant: Robert Mack ,  Timothy Chen

Inventor： Robert Mack ,  Timothy Chen

IPC: H03L1/00

CPC classification number: G06F1/022 ,  G06F1/0328 ,  G06F1/08 ,  H03B28/00 ,  H03B2200/0088 ,  H03L1/00 ,  H03L7/0994

Abstract: A method for compensating NCO jitter by changing a step value used to increment an accumulator in the NCO to make up for inaccuracies, or jitters. In one approach, a remainder in the accumulator may be monitored and a compensated clock close to the current edge of an ideal clock may be generated. In another approach, a compensated clock close to the next edge of the ideal clock may be generated after the current edge of the ideal clock is missed. The step value may be stored in a memory, which may be a register. A jitter compensator may include a comparator for monitoring the remainder in the accumulator or a detector for detecting whether an ideal clock has been missed. The jitter compensator may also change the step value to a step value for a faster clock to compensate jitter.

Abstract translation: 一种用于通过改变用于增加NCO中的累加器的步长值来补偿NCO抖动以补偿不准确或不稳定的方法。 在一种方法中，可以监视累加器中的余数，并且可以产生接近理想时钟的当前边缘的补偿时钟。 在另一种方法中，在理想时钟的当前边缘被错过之后，可以产生靠近理想时钟的下一个边缘的补偿时钟。 步数值可以存储在可以是寄存器的存储器中。 抖动补偿器可以包括用于监视累加器中的余数的比较器或用于检测是否错过理想时钟的检测器。 抖动补偿器还可以将步长值改变为更快时钟的步进值以补偿抖动。

公开(公告)号：US20100118894A1

公开(公告)日：2010-05-13

申请号：US12268008

申请日：2008-11-10

Applicant: James AWEYA ,  Michel OUELLETTE ,  Delfin Y. MONTUNO

Inventor： James AWEYA ,  Michel OUELLETTE ,  Delfin Y. MONTUNO

IPC: H04J3/06

CPC classification number: H04L7/0079 ,  G06F1/0328 ,  H03L7/0805 ,  H03L7/085 ,  H03L7/089 ,  H03L2207/50 ,  H04J3/0632 ,  H04J3/0658

Abstract: A method, system and master service interface transfer differential timing over a packet network. The transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Abstract translation: 一种方法，系统和主服务接口通过分组网络传输差分定时。 发送业务接口接收业务时钟，通过网络背板耦合到接收业务接口。 提供主参考时钟来对网络背板进行时间。 主参考时钟和服务时钟用于合成连接到发送服务接口的业务时钟的副本。 生成服务时钟和服务时钟的合成副本之间的误差的第一个控制字，并经由分组通过网络背板发送。 第一个控制字与主参考时钟一起用于重新创建用于定时接收服务接口的服务时钟。

公开(公告)号：US07702707B2

公开(公告)日：2010-04-20

申请号：US10548115

申请日：2004-02-12

Applicant: Neil Thomas ,  Peter John Howlett Fox

Inventor： Neil Thomas ,  Peter John Howlett Fox

IPC: G06F1/02

CPC classification number: G06F1/0328

Abstract: A waveform generator for generating a smooth version of an original waveform which contains abrupt transitions, includes a phase accumulator incremented at successive sampling times to produce an output representative of the phase of the original waveform, a phase scaler arranged to convert the residual contents of the accumulator following a transition from phase to time, computing means responsive to the time to calculate a number of samples along a smooth transition, each offset by that time from the sampling times, and a sequencer to replace the otherwise abrupt transition with the sequence of samples from the computed smooth transition.

Abstract translation: 用于产生包含突变的原始波形的平滑版本的波形发生器包括在连续采样时间递增的相位累加器，以产生代表原始波形的相位的输出;相位定标器，被布置成将 累加器在相对于时间的转变之后，响应于时间来计算沿着平滑过渡的每个样本的时间的计算装置，每个样本从采样时间偏移到该时间，以及定序器以用样本序列代替另外的突变过渡 从计算的平滑过渡。

公开(公告)号：US07599977B2

公开(公告)日：2009-10-06

申请号：US11204674

申请日：2005-08-16

Applicant: Danny F. Ammar

Inventor： Danny F. Ammar

IPC: G06F1/02

CPC classification number: G06F1/0328 ,  G06F1/0342 ,  G06F2211/902 ,  H03L7/16

Abstract: A direct digital synthesizer (DDS) has reduced spurious signals and includes a DDS core that produces a digital representation of a signal to be synthesized. A plurality of DDS circuits are operatively connected to the DDS core, each having a digital-to-analog converter connected to the DDS core for receiving the digital representation and converting it into a signal. A modulator is operatively connected to an oscillator circuit and digital-to-analog converter for receiving signals from the digital-to-analog converter and producing a modulated output signal. The individual frequencies of the respective DDS circuits are randomly and continuously changed from each other. A mixer receives and mixes the modulated output signals from the plurality of DDS circuits to create a mixed output signal at a selected and fixed frequency.

Abstract translation: 直接数字合成器（DDS）具有减少的杂散信号，并且包括产生要合成的信号的数字表示的DDS核。 多个DDS电路可操作地连接到DDS核心，每个DDS核心具有连接到DDS核心的数模转换器，用于接收数字表示并将其转换成信号。 调制器可操作地连接到振荡器电路和数 - 模转换器，用于从数模转换器接收信号并产生调制输出信号。 相应的DDS电路的各个频率彼此随机和连续地变化。 混频器接收并混合来自多个DDS电路的调制输出信号，以选择和固定的频率创建混合输出信号。

公开(公告)号：US20090121796A1

公开(公告)日：2009-05-14

申请号：US11937362

申请日：2007-11-08

Applicant: Jeffery S. Patterson

Inventor： Jeffery S. Patterson

IPC: H03B27/00

CPC classification number: H03K5/156 ,  G06F1/0328 ,  H03K2005/00052

Abstract: A polyphase numerically controlled oscillator is disclosed. An input signal is received at a phase accumulator. The phase accumulator provides a phase to a phase interpolator. The phase interpolator then provides a plurality of output phases. The plurality of output phases are provided to a plurality of phase to amplitude converters. Each of said plurality of phase to amplitude converters process one of said plurality of output phases.

Abstract translation: 公开了一种多相数控振荡器。 在相位累加器处接收输入信号。 相位累加器向相位内插器提供相位。 然后，相位插值器提供多个输出相位。 多个输出相位被提供给多个相位到幅度转换器。 所述多个相位幅度转换器中的每一个处理所述多个输出相位之一。

公开(公告)号：US20070067123A1

公开(公告)日：2007-03-22

申请号：US11231223

申请日：2005-09-19

Applicant: Roger Jungerman

Inventor： Roger Jungerman

IPC: G01R13/02

CPC classification number: G06F1/0328 ,  G06F1/0321 ,  G06F1/0342

Abstract: An advanced arbitrary waveform generator (“AAWG”) for producing an arbitrary waveform is disclosed. The AAWG may include a direct digital synthesis (“DDS”) module in signal communication with a sequence memory and a multiplication module in signal communication with both the DDS module and a waveform memory, where the multiplication module receives signal waveform data from the waveform memory and multiplies the received signal waveform data with a DDS output signal to produce the arbitrary waveform signal.

Abstract translation: 公开了用于产生任意波形的高级任意波形发生器（“AAWG”）。 AAWG可以包括与序列存储器进行信号通信的直接数字合成（“DDS”）模块和与DDS模块和波形存储器进行信号通信的乘法模块，其中乘法模块从波形存储器接收信号波形数据 并将接收到的信号波形数据与DDS输出信号相乘以产生任意波形信号。

公开(公告)号：US20060282715A1

公开(公告)日：2006-12-14

申请号：US11396169

申请日：2006-03-31

Applicant: Joachim Moll ,  Martin Muecke

Inventor： Joachim Moll ,  Martin Muecke

IPC: G06F11/00

CPC classification number: G06F1/0328 ,  G06F1/022 ,  H03K5/05

Abstract: The invention relates to a signal generator for generating a sequence of digital values according to a reference clock signal, comprising at least one input terminal for receiving a an increment signal and an offset signal, a start value circuit adapted for determining a counter start value on the base of the offset signal and the increment signal, a counter being adapted to be set to the start value, and to change the counter position at each cycle of the reference clock signal to a new value according to the increment signal until a defined value is achieved, and an output terminal for outputting the counter values.

Abstract translation: 本发明涉及一种用于根据参考时钟信号生成数字值序列的信号发生器，包括用于接收增量信号和偏移信号的至少一个输入端子，适于确定计数器起始值的起始值电路 偏移信号的基极和增量信号，适于被设置为起始值的计数器，并且根据增量信号将参考时钟信号的每个周期的计数器位置改变为新值，直到定义的值 以及用于输出计数器值的输出端子。

公开(公告)号：US07109808B1

公开(公告)日：2006-09-19

申请号：US11007613

申请日：2004-12-07

Applicant: Robert Pelt

Inventor： Robert Pelt

IPC: H03B1/04

CPC classification number: G06F1/0328 ,  G06F1/0342

Abstract: A polyphase numerically controlled oscillator (PNCO) is defined to include a plurality of sub-numerically controller oscillators (SNCO's). Each SNCO is capable of receiving a clock signal at a first clock rate and an assigned phase offset signal. Each SNCO is configured to generate a digital waveform for the assigned phase offset signal. The PNCO also includes a plurality of frequency multipliers for generating a frequency multiplied representation of the digital waveform generated by each SNCO. The PNCO further includes a multiplexer configured to receive output from each of the frequency multipliers according to the first clock rate. The multiplexer is further configured to receive a select signal, wherein the select signal triggers the multiplexer at a second clock rate.

Abstract translation: 多相数控振荡器（PNCO）被定义为包括多个子数字控制振荡器（SNCO）。 每个SNCO能够以第一时钟速率和所分配的相位偏移信号接收时钟信号。 每个SNCO被配置为产生用于所分配的相位偏移信号的数字波形。 PNCO还包括用于产生由每个SNCO产生的数字波形的倍频表示的多个频率乘法器。 PNCO还包括被配置为根据第一时钟速率从每个频率乘法器接收输出的多路复用器。 多路复用器还被配置为接收选择信号，其中选择信号以第二时钟速率触发多路复用器。