利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

1177 records (took 0.029 seconds)

    Method for removing ATM cells from an ATM communications device
    42.
    发明授权
    Method for removing ATM cells from an ATM communications device 有权
    从ATM通信设备中移除ATM信元的方法

    公开(公告)号：US07145907B1

    公开(公告)日：2006-12-05

    申请号：US09623775

    申请日：1999-03-08

    Applicant: Herbert Heiss ,  Raimar Thudt

    Inventor： Herbert Heiss ,  Raimar Thudt

    IPC: H04L12/56 ,  H04L12/28 ,  H04L12/26

    CPC classification number: H04Q11/0478 ,  H04L2012/5647 ,  H04L2012/5667 ,  H04L2012/5681

    Abstract: A method for removal of ATM cells (2, 6) from an ATM communications device wherein ATM cells (2, 3, 5, 6) are respectively allocated in pluralities to a common frame (8, 9), whereby all ATM cells (2 . . . 6) of a frame (9) whose first ATM cell (2) is in the waiting list (1) are removed from a waiting list (1) for the administration of a sequence of ATM cells (2, 3, 4, 5, 6). The method makes it possible to quickly and efficiently create space for cells having a higher priority in the ATM communications device.

    Abstract translation: 一种用于从ATM通信设备移除ATM信元（2,6）的方法，其中ATM信元（2,3,5,6）分别分配多个到公共帧（8,9），由此所有ATM信元（2 从等待列表（1）中删除其第一ATM信元（2）位于等待列表（1）中的帧（9）的...（6），用于管理一系列ATM信元（2,3,4 ，5,6）。 该方法使得可以在ATM通信设备中快速有效地创建具有较高优先级的小区的空间。

    Apparatus and method for processing cells in a communications system
    45.
    发明申请
    Apparatus and method for processing cells in a communications system 失效
    用于处理通信系统中的小区的设备和方法

    公开(公告)号：US20060221976A1

    公开(公告)日：2006-10-05

    申请号：US11095769

    申请日：2005-03-31

    Applicant: Kenneth Isley

    Inventor： Kenneth Isley

    IPC: H04J3/06 ,  H04J3/24 ,  H04L12/56 ,  H04L12/28

    CPC classification number: H04L12/5601 ,  H04L2012/5649 ,  H04L2012/565 ,  H04L2012/5652 ,  H04L2012/5654 ,  H04L2012/5681

    Abstract: An apparatus for interfacing with a cell delay variation buffer and a re-assembly memory buffer includes a header and sequence number processing module that can interface with the cell delay variation buffer and a re-assembly processing module that can interface with the re-assembly memory buffer. The header and sequence number processing module causes payloads from the cells to be stored in annotated form in the cell delay variation buffer and then extracted. Payload information from the extracted annotated payload can be passed to the re-assembly processing module which causes it to be stored in the re-assembly memory buffer and extracted therefrom as needed. By splitting the cell delay variation and re-assembly buffer functions, less expensive commodity memory can be used for the cell delay variation buffer function.

    Abstract translation: 用于与单元延迟变化缓冲器和重新组装存储器缓冲器接口的装置包括可与单元延迟变化缓冲器接口的报头和序列号处理模块以及可与重新组装存储器接口的重组处理模块 缓冲。 标题和序列号处理模块使得来自单元的有效载荷以注释形式存储在单元延迟变化缓冲器中，然后提取。 来自提取的有注释的有效载荷的有效载荷信息可以被传递到重新组装处理模块，该模块将其存储在重新组装的存储器缓冲器中并且根据需要从其中提取。 通过拆分单元延迟变化和重新组装缓冲功能，便宜的商品存储器可用于单元延迟变化缓冲功能。

    Processor architecture and a method of processing
    46.
    发明授权
    Processor architecture and a method of processing 有权
    处理器架构和一种处理方法

    公开(公告)号：US07116680B1

    公开(公告)日：2006-10-03

    申请号：US09798112

    申请日：2001-03-02

    Applicant: David B Kramer ,  David P Sonnier

    Inventor： David B Kramer ,  David P Sonnier

    IPC: H04L12/56 ,  H04J3/22

    CPC classification number: H04L47/56 ,  H04L12/5601 ,  H04L47/36 ,  H04L47/50 ,  H04L49/3072 ,  H04L49/309 ,  H04L49/608 ,  H04L2012/5679 ,  H04L2012/5681

    Abstract: A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted independent of the process to modify or transform the packet. The packet could be an ATM cell, it could be a fabric cell, or it could be a portion of a frame-based transmission of the packet. As a result, the transmit queue need only determine how many times (times to transmit (TTT)) to schedule transmission of part of the packet. The determined TTT from the transit queue takes into account the packet-based modifications that will be performed on the packet. The TTT is used to determine how many cells the packet needs to be divided into. In another illustrative embodiment, the number of cells or the TTT is determined prior to adding or removing data from the packet. In a further illustrative embodiment, the transmit queue is separate from the circuitry that modifies the packet. In other words, determining the TTT for a packet is separate from the process of modifying the packet for transmission.

    Abstract translation: 一种简化高速调度器实现的过程和架构。 传统的基于分组的调度器工作包的长度。 相反，本发明使用发送队列，其确定分组的一部分需要多少次发送，独立于修改或转换分组的处理。 分组可以是ATM信元，它可以是结构小区，或者它可以是分组的基于帧的传输的一部分。 因此，发送队列只需要确定多少次（传输次数（TTT））来调度部分数据包的传输。 来自传输队列的确定的TTT考虑了将在分组上执行的基于分组的修改。 TTT用于确定数据包需要分成多少个单元。 在另一示例性实施例中，在从分组添加或移除数据之前确定小区数目或TTT。 在另一说明性实施例中，发送队列与修改分组的电路分离。 换句话说，确定分组的TTT与修改分组以进行传输的过程是分开的。

    Hardware self-sorting scheduling queue
    47.
    发明授权
    Hardware self-sorting scheduling queue 有权

    公开(公告)号：US07113510B2

    公开(公告)日：2006-09-26

    申请号：US10087722

    申请日：2002-03-01

    Applicant: Xinming Allen Lin

    Inventor： Xinming Allen Lin

    IPC: H04L12/28

    CPC classification number: H04L47/6215 ,  H04L47/24 ,  H04L47/2408 ,  H04L47/2433 ,  H04L47/50 ,  H04L2012/5681 ,  H04L2012/5684

    Abstract: The scheduling queue of the present invention is configured as a systolic array utilizing self-sorting scheduling cells to sort information packets based upon previously assigned priorities, while at the same time yielding a small constant latency independent of the length of the queue. The scheduling queue of the present invention is effective in supporting various Quality of Service (QoS) policies and algorithms, including both Differentiated Services (DiffServ) and Integrated Services (IntServ) having an arbitrary number of flows.

    Multicast cell buffer for network switch
    49.
    发明授权
    Multicast cell buffer for network switch 有权

    公开(公告)号：US07110405B2

    公开(公告)日：2006-09-19

    申请号：US09955615

    申请日：2001-09-18

    Applicant: Robert J. Divivier

    Inventor： Robert J. Divivier

    IPC: H04L12/56

    CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/203 ,  H04L49/405 ,  H04L2012/5681

    Abstract: An input port for a network switch includes a cell buffer for receiving incoming unicast and multicast cells and for writing each cell into an internal cell memory. The cell buffer thereafter forwards each unicast cell from the cell memory to one network switch output port and forwards a separate copy of each multicast cell to each of several network switch output ports. When the cell buffer writes a unicast cell to the cell memory, it sends a pointer to the storage location of the unicast cell to a queue manager. When the cell buffer writes a multicast cell to the cell memory, it sends several pointers to the queue manager, one for each output port that is to receive a copy of the multicast cell, with each pointer pointing not to the multicast cell's storage location but to an empty storage location in the cell memory. The cell buffer also maintains a database relating each pointer it sent to the queue manager to an actual storage location of a unicast or multicast cell. The queue manager queues the pointers an order in which cells are to be forwarded from the cell buffer, and thereafter returns a pointer to the cell buffer whenever the cell buffer is to forward a unicast cell or a copy of a multicast cell from the cell memory. The cell buffer applies each returned pointer to the database to determine the actual location of the unicast or multicast cell to be forwarded.

    System and method of avoiding cell disposal in buffer
    50.
    发明授权
    System and method of avoiding cell disposal in buffer 失效
    避免细胞在缓冲液中的处置的系统和方法

    公开(公告)号：US07106745B2

    公开(公告)日：2006-09-12

    申请号：US11167582

    申请日：2005-06-28

    Applicant: Yuichi Kusumoto

    Inventor： Yuichi Kusumoto

    IPC: H04L12/28

    CPC classification number: H04L49/552 ,  H04L12/5601 ,  H04L43/16 ,  H04L47/50 ,  H04L47/522 ,  H04L47/6225 ,  H04L47/6255 ,  H04L2012/5648 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/568 ,  H04L2012/5681 ,  H04L2012/5682

    Abstract: A cell disposal avoidance system is provided that can avoid disposal of the cells resided in the QoS buffer when a traffic of a specific QoS class in an ATM switch increases. The ATM switch includes a storage cell number monitor, a software data section 813, and a software controller 812. The storage cell number monitor monitors congestion of plural QoS buffers in the buffer 3, 5. The software data section 813 stores a cell reading priority (WRR value) attached for each QoS buffer. The software controller 812 dynamically changes the WRR value when congestion of a QoS buffer is in a congestion state (at generation of cell disposal or buffer congestion alarm) and increases the WRR value of the QoS buffer in a cell disposal state. Cells are divided in a time division mode according to the weight of the WRR value and read in a round format from the QoS buffer. The ATM switch resets the WRR value to an initial value when the congestion of the QoS buffer ceases.

    Abstract translation: 提供了一种在ATM交换机中特定QoS级别的流量增加时能够避免驻留在QoS缓冲器中的小区的处理的小区处理回避系统。 ATM交换机包括存储单元号码监视器，软件数据部分813和软件控制器812。 存储单元号监视器监视缓冲器3,5中的多个QoS缓冲器的拥塞。 软件数据部分813存储为每个QoS缓冲器附加的单元读取优先级（WRR值）。 软件控制器812在QoS缓冲器的拥塞处于拥塞状态（在生成小区处理或缓冲拥塞告警）时动态地​​改变WRR值，并增加小区处理状态下的QoS缓冲区的WRR值。 根据WRR值的权重，以时分方式划分小区，并从QoS缓冲区中以循环格式读取。 当QoS缓存的拥塞停止时，ATM交换机将WRR值重置为初始值。

Patent Agency Ranking