公开(公告)号：US20100329364A1

公开(公告)日：2010-12-30

申请号：US12826424

申请日：2010-06-29

Applicant: Salvatore Giombanco ,  Giovanni Lombardo ,  Salvatore Tumminaro ,  Filippo Marino

Inventor： Salvatore Giombanco ,  Giovanni Lombardo ,  Salvatore Tumminaro ,  Filippo Marino

IPC: H04L7/00 ,  H04B3/00

CPC classification number: H04B1/16 ,  H04L7/0008 ,  H04L25/0264 ,  H04L25/0268 ,  H04L27/02

Abstract: A transmission and reception apparatus for at least one digital data signal is described. The digital data signal is characterized by two logical levels, first and second logical levels, with said second logical level higher than the first logical level. The apparatus comprises a transmitter, a receiver and a galvanically isolated interface arranged between the transmitter and the receiver; said transmitter, receiver and interface are arranged so as to form a two-level isolated digital channel and the transmitter comprises a block adapted to send a clock signal to the receiver. The receiver comprises, a circuit adapted to synchronize the receiver and the transmitter using the received clock signal and a circuit adapted to memorize information related to the synchronization in a storage element to hold the synchronization while the receiver is receiving said digital data. The transmitter block is adapted to send said digital data signal after the synchronization of the receiver and transmitter.

Abstract translation: 描述用于至少一个数字数据信号的发送和接收装置。 数字数据信号的特征在于两个逻辑电平，第一和第二逻辑电平，其中所述第二逻辑电平高于第一逻辑电平。 该装置包括发射机，接收机和布置在发射机和接收机之间的电隔离接口; 所述发射机，接收机和接口被布置成形成两级隔离数字信道，并且发射机包括适于向接收机发送时钟信号的块。 接收机包括：适于使用所接收的时钟信号来同步接收机和发射机的电路;以及适于在存储元件中存储与同步有关的信息以在接收机正在接收所述数字数据时保持同步的电路。 发射机模块适于在接收机和发射机同步之后发送所述数字数据信号。

公开(公告)号：US07804793B1

公开(公告)日：2010-09-28

申请号：US11862582

申请日：2007-09-27

Applicant: Mickey S. Felton

Inventor： Mickey S. Felton

IPC: H04B1/52 ,  H04L5/00 ,  G06F3/00 ,  G06F13/00

CPC classification number: G06F13/4295 ,  H04L5/06 ,  H04L25/0264 ,  H04L25/0276

Abstract: A relatively low frequency signal—e.g. RS-232—is coupled to and extracted from a communication link that carries both a high frequency continuous signal and burst mode signal having bursts occurring at one or more frequencies—e.g. SAS with OOB signaling. The communication link has a differential coupling which differentially couples onto a first pair of conductors a continuous signal at a continuous rate and a burst mode signal having bursts occurring at one or more frequencies. The communication link also has a common mode coupling which common mode couples a second signal onto the first pair of conductors. A high pass filter coupled to the first pair of conductors extracts the continuous signal and the burst mode signal from the first pair of conductors. A low pass filter coupled to the first pair of conductors extracts the second signal from the first pair of conductors.

Abstract translation: 相对低频的信号 - 例如 RS-232耦合到通信链路并从其提取，该通信链路携带具有以一个或多个频率出现的突发的高频连续信号和突发模式信号，例如， SAS与OOB信令。 通信链路具有差分耦合，其以连续速率差分耦合到第一对导体上的连续信号，并且具有以一个或多个频率发生突发的突发模式信号。 通信链路还具有共模耦合，该共模模式将第二信号耦合到第一对导体上。 耦合到第一对导体的高通滤波器从第一对导体提取连续信号和突发模式信号。 耦合到第一对导体的低通滤波器从第一对导体提取第二信号。

公开(公告)号：US20100142297A1

公开(公告)日：2010-06-10

申请号：US12494381

申请日：2009-06-30

Applicant: Dong Uk LEE ,  Ji Yeon YANG

Inventor： Dong Uk LEE ,  Ji Yeon YANG

IPC: G11C7/00 ,  H03K19/003

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H04L25/0264

Abstract: A data driver is presented in which the data driver includes a termination/pull-up driver and a pull-down driver. The termination/pull-up driver is configured to perform a termination operation and a pull-up operation at the same time for a data output terminal during an active interval of a semiconductor memory. The pull-down driver is configured to be activated when the semiconductor memory performs a read operation, and configured to pull down the output terminal in response to a level of an input data.

Abstract translation: 提出了一种数据驱动器，其中数据驱动器包括终端/上拉驱动器和下拉驱动器。 终端/上拉驱动器被配置为在半导体存储器的有效间隔期间同时为数据输出端子执行终止操作和上拉操作。 下拉驱动器被配置为当半导体存储器执行读取操作时被激活，并且被配置为响应于输入数据的电平来下拉输出端子。

公开(公告)号：US20090302806A1

公开(公告)日：2009-12-10

申请号：US12097463

申请日：2006-12-15

Applicant: Heribert Lindlar ,  Stefan Sattler

Inventor： Heribert Lindlar ,  Stefan Sattler

IPC: H02J7/00

CPC classification number: H04W52/0229 ,  H04L25/0264 ,  Y02D70/00

Abstract: Control circuitry for providing an interface between connectable terminal and peripheral device circuitry, wherein the peripheral device circuitry comprises a bus line for transferring data and power between the peripheral device circuitry and the terminal device circuitry; a charge storage device arranged to receive power from the terminal device circuitry over the bus line and to supply the power to the control circuitry; wherein the control circuitry is operable to connect the charge storage device to the bus line to receive power for storage in response to the terminal device circuitry transmitting a first data value represented by a higher voltage level and to disconnect the charge storage device from the bus line in response to the terminal device circuitry transmitting a second data value represented by a lower voltage level, to prevent the charge storage device from discharging over the bus.

Abstract translation: 用于在可连接终端和外围设备电路之间提供接口的控制电路，其中所述外围设备电路包括用于在所述外围设备电路和所述终端设备电路之间传送数据和电力的总线; 电荷存储装置，被布置成通过总线从终端装置电路接收电力，并向控制电路供电; 其中所述控制电路可操作以将所述电荷存储装置连接到所述总线以接收用于存储的电力，以响应于所述终端装置电路传输由较高电压电平表示的第一数据值，并将所述电荷存储装置与所述总线断开 响应于终端设备电路发送由较低电压电平表示的第二数据值，以防止电荷存储设备在总线上放电。

公开(公告)号：US07606537B2

公开(公告)日：2009-10-20

申请号：US10933762

申请日：2004-09-03

Applicant: Colin Dugald Brodhead

Inventor： Colin Dugald Brodhead

IPC: H04B1/69

CPC classification number: H04L25/0264 ,  H04L27/02

Abstract: A system and method of encoding and transmitting data includes a data receiver/carrier transmitter which transmits a sinusoidal carrier signal to a data source/carrier receiver. The data source encodes at least one transmission channel during a corresponding period. The carrier is reflected back to the data receiver with an amplitude proportional to the degree of applied impedance such that the total amplitude of the transmitted and reflected cycles represents encoded data, yet the underlying carrier signal remains an un-modulated sinusoid.

Abstract translation: 编码和发送数据的系统和方法包括将数据接收机/载波发射机发射到数据源/载波接收机的正弦载波信号。 数据源在相应的周期期间对至少一个传输信道进行编码。 载波以与施加的阻抗的程度成正比的幅度被反射回数据接收机，使得发送和反射周期的总幅度表示编码数据，而下行的载波信号保持为未调制的正弦波。

公开(公告)号：US20090206879A1

公开(公告)日：2009-08-20

申请号：US12379289

申请日：2009-02-18

Applicant: Toru Ishikawa

Inventor： Toru Ishikawa

IPC: H03K19/094

CPC classification number: H04L25/0264 ,  H01L2224/48137 ,  H04L25/0278

Abstract: A signal transmission circuit includes first and second power source wirings, and a plurality of differential circuits connected in series between the first and second power source wirings. A signal transmission system includes a plurality of pairs of signal wirings, an output circuit supplying a differential signal to each of the pairs of signal wirings, and an input circuit receiving the differential signals via the pairs of signal wirings, wherein the output circuit includes first and second power source wirings, and a plurality of differential output circuits connected in series between the first and second power source wirings, and the input circuit includes a plurality of differential input circuits respectively corresponding to the differential output circuits.

Abstract translation: 信号传输电路包括第一和第二电源布线，以及串联连接在第一和第二电源布线之间的多个差分电路。 信号传输系统包括多对信号布线，输出电路向每对信号布线提供差分信号，以及输入电路经由信号配线对接收差分信号，其中输出电路包括第一 和第二电源布线，以及串联连接在第一和第二电源布线之间的多个差分输出电路，并且输入电路包括分别对应于差分输出电路的多个差分输入电路。

公开(公告)号：US07551020B2

公开(公告)日：2009-06-23

申请号：US11755955

申请日：2007-05-31

Applicant: Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

Inventor： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Antonio M. Marques ,  Bernard L. Morris

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H03K19/00384 ,  H04L5/16 ,  H04L25/0264

Abstract: A compensation circuit for compensating an output impedance of at least a first MOS device over PVT variations to which the first MOS device may be subjected includes a first current source generating a first current having a value which is substantially constant and a second current source generating a second current having a value which is programmable as a function of at least one control signal presented to the second current source. A comparator is connected to respective outputs of the first and second current sources and is operative to measure a difference between the respective values of the first and second currents and to generate an output signal indicative of relative magnitudes of the first current and the second current. A processor connected in a feedback arrangement between the comparator and the second current source receives the output signal generated by the comparator and generates the control signal for controlling the second current as a function of the output signal. The processor is operative to control the value of the second current so that the second current is substantially equal to the first current.

Abstract translation: 用于补偿至少第一MOS器件的输出阻抗的补偿电路，其中PVT变化对其可能经受的PVT变化包括：第一电流源，其产生具有基本恒定值的第一电流和产生第一MOS器件的第二电流源 第二电流具有可被编程为呈现给第二电流源的至少一个控制信号的函数的值。 比较器连接到第一和第二电流源的相应输出，并且可操作以测量第一和第二电流的相应值之间的差，并产生指示第一电流和第二电流的相对幅度的输出信号。 连接在比较器和第二电流源之间的反馈装置中的处理器接收比较器产生的输出信号，并产生用于根据输出信号控制第二电流的控制信号。 处理器可操作以控制第二电流的值，使得第二电流基本上等于第一电流。

公开(公告)号：US20080273623A1

公开(公告)日：2008-11-06

申请号：US12103823

申请日：2008-04-16

Applicant: Hoe-ju CHUNG ,  Jung-bae LEE

Inventor： Hoe-ju CHUNG ,  Jung-bae LEE

IPC: H04L27/00

CPC classification number: H04L25/0264 ,  H04L25/0272

Abstract: In a communication system, data is selectively transmitted using single-ended or differential signaling. The data is transmitted in relation to a plurality of clock signals having different relative phases. When the data is transmitted using single-ended signaling, data on adjacent signal lines undergo logic transitions at different times in relation to the plurality of clock signals.

Abstract translation: 在通信系统中，使用单端或差分信令有选择地发送数据。 相对于具有不同相对相位的多个时钟信号发送数据。 当使用单端信令发送数据时，相邻信号线上的数据相对于多个时钟信号在不同时刻进行逻辑转换。

公开(公告)号：US07382597B2

公开(公告)日：2008-06-03

申请号：US10547728

申请日：2004-03-02

Applicant: Clemens G. J. De Haas

Inventor： Clemens G. J. De Haas

IPC: H02H9/00

CPC classification number: H04L25/0272 ,  H04B15/00 ,  H04L25/0264 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/03878

Abstract: A bondwire decoupling filter 300 for filtering RF noise from a transceiver bus 330 of a transceiver 303 connected a device 302 to be protected from RF noise. The filter includes an external capacitor 315 adapted to receive an output from a device 302 to be protected from the RF noise; a first pair of bondwires 305, 307 each having respective first and second ends, and the first pair of bondwires is connected to the external capacitor 315 at respective first ends. A first bondwire 307 of the first pair of bondwires 305, 307 is connected to an output of a voltage regulator 302, and a second bondwire 305 of said first pair of bondwires being connected to the transceiver bus 330 at respective second ends. A second pair of bondwires 310, 312 each having respective first and second ends, are connected to a ground at respective first ends, and connected respectively to a voltage regulator 302 and a transceiver bus 330 at respective second ends.

Abstract translation: 用于过滤来自收发器303的收发机总线330的RF噪声的键线去耦滤波器300，该收发机303连接到要被保护的RF噪声的设备302。 滤波器包括适于接收来自设备302的输出以防止RF噪声的外部电容器315; 各自具有相应的第一和第二端的第一对键合线305,307和第一对键合线在相应的第一端连接到外部电容器315。 第一对键合线305,307的第一接合线307连接到电压调节器302的输出，并且所述第一对键合线的第二接合线305在相应的第二端连接到收发器总线330。 每个具有相应的第一和第二端的第二对键合线310,312在相应的第一端处连接到地，并且在相应的第二端分别连接到电压调节器302和收发器总线330。

公开(公告)号：US20080112503A1

公开(公告)日：2008-05-15

申请号：US11560257

申请日：2006-11-15

Applicant: Daniel N. De Araujo ,  Moises Cases ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

Inventor： Daniel N. De Araujo ,  Moises Cases ,  Bradley D. Herrman ,  Erdem Matoglu ,  Bhyrav M. Mutnury ,  Pravin S. Patel ,  Nam H. Pham

IPC: H04L25/03

CPC classification number: H04L25/0264 ,  H04L25/0286

Abstract: An apparatus, system, and method are disclosed for dynamic phase equalization in a communication channel. A transmitter history module stores a plurality of bits from a data stream that is transmitted through the communication channel. A transmitter detection module detects a pre-transition bit of a first value that is preceded in the data stream by at least one bit of the first value and followed by a transition bit with a second value. A driver module transmits the data stream by driving the communication channel. A transition module pre-drives the communication channel to the second voltage of the transition bit during a bit time interval of the pre-transition bit.

Abstract translation: 公开了用于通信信道中的动态相位均衡的装置，系统和方法。 发射机历史模块从通过通信信道发送的数据流存储多个比特。 发射机检测模块检测在数据流中前面的第一值的前转换比特的第一值的至少一个比特，然后跟随具有第二值的转换比特。 驾驶员模块通过驱动通信信道来发送数据流。 转换模块在预转换位的位时间间隔期间将通信通道预驱动到转换位的第二电压。