公开(公告)号：US06624680B2

公开(公告)日：2003-09-23

申请号：US09998827

申请日：2001-12-03

申请人： Stephen R. Schenck

发明人： Stephen R. Schenck

IPC分类号： H03H1126

CPC分类号： H03K19/00384 ,  H03K5/133 ,  H03K2005/0013

摘要： In one embodiment, a digital circuit element has a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element. In another embodiment, a digital circuit element may include an input node, an output node, and at least one gate coupling the input node and the output node. A plurality of possible voltage transition curves may be associated with a corresponding change of a first voltage at the input node over time, each voltage transition curve being determined by a corresponding supply voltage and the curves intersecting within a relatively narrow range of voltages. The gate may be operable to change a second voltage at the output node in response to the first voltage reaching a threshold voltage of the gate, and the threshold voltage may be set within the relatively narrow range of voltages in which the voltage transition curves intersect in order to reduce the dependence of the propagation delay on the supply voltage. In yet another embodiment, a digital circuit element having a propagation delay that is substantially constant over a range of supply voltages applied to the digital circuit element includes an input node, an output node, and at least one gate coupling the input node and the output node. The gate is operable to change a first voltage at the output node in response to a second voltage at the input node reaching a threshold voltage of the gate, and the threshold voltage of the gate is set such that a delay separating an initial change in the first voltage from an initial change in the second voltage is substantially constant over a range of supply voltages applied to the digital circuit element.

公开(公告)号：US06617903B2

公开(公告)日：2003-09-09

申请号：US09901131

申请日：2001-07-10

申请人： Yukio Kawamura

发明人： Yukio Kawamura

IPC分类号： H03H1126

CPC分类号： H03K17/166 ,  H03K17/163 ,  H03K19/0013

摘要： An inverter circuit includes a first transistor connected between an input terminal and a gate of a second transistor, a second transistor connected between power supply voltage and an output terminal, a third transistor connected between an input terminal and a gate of a fourth transistor and a fourth transistor connected between a ground and the output terminal.

摘要翻译： 逆变器电路包括连接在第二晶体管的输入端和栅极之间的第一晶体管，连接在电源电压和输出端之间的第二晶体管，连接在第四晶体管的输入端和栅极之间的第三晶体管， 第四晶体管连接在地和输出端之间。

公开(公告)号：US06614278B2

公开(公告)日：2003-09-02

申请号：US09870265

申请日：2001-05-29

申请人： Kyo-hyoun Kim ,  Dae-Hyun Chung

发明人： Kyo-hyoun Kim ,  Dae-Hyun Chung

IPC分类号： H03H1126

CPC分类号： H03K5/08 ,  H03H11/265 ,  H03K5/13 ,  H03K2005/00071

摘要： A delay circuit has an input node receives an input pulsed signal. A buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. Two similar branches are used, one for controlling delays in the rising transitions and one for controlling delays in the falling transitions. For each branch, a reference terminal carries a reference voltage for biasing the floating node. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor. An optional phase detector and delay code generator may be in a feedback arrangement, for continuously adjusting the reference voltages.

公开(公告)号：US06593791B1

公开(公告)日：2003-07-15

申请号：US10115359

申请日：2002-04-03

申请人： Sharon Lynn Weintraub

发明人： Sharon Lynn Weintraub

IPC分类号： H03H1126

CPC分类号： H03K5/135

摘要： A digital delay circuit employs a stable reference clock signal, delayed by a reference delay line, to obtain information related to delay characteristics of a matching input delay line. An input clock signal is delayed by the input delay line, which provides a plurality of variously delayed input clock signals based upon the input clock signal. The reference delay line provides a plurality of variously delayed reference clock signals based upon the stable reference clock signal; the delayed reference clock signals convey information related to the operating characteristics of both delay lines. In response to such information, one of the delayed input clock signals can be selected as a delayed clock output. The reference and input delay lines are configured such that the delay circuit consistently generates a delayed clock output having an actual delay that falls within a specified range of delay.

摘要翻译： 数字延迟电路使用延迟参考延迟线的稳定参考时钟信号，以获得与匹配输入延迟线的延迟特性相关的信息。 输入时钟信号被输入延迟线延迟，输入延迟线基于输入的时钟信号提供多个不同延迟的输入时钟信号。 参考延迟线基于稳定的参考时钟信号提供多个不同延迟的参考时钟信号; 延迟的参考时钟信号传送与两个延迟线的操作特性有关的信息。 响应于这样的信息，延迟输入时钟信号之一可被选择为延迟的时钟输出。 参考和输入延迟线被配置为使得延迟电路一致地产生具有落在指定延迟范围内的实际延迟的延迟时钟输出。

公开(公告)号：US06590434B2

公开(公告)日：2003-07-08

申请号：US10191413

申请日：2002-07-10

申请人： Hoe-ju Chung ,  Tae-seong Jang ,  Kyu-hyoun Kim

发明人： Hoe-ju Chung ,  Tae-seong Jang ,  Kyu-hyoun Kim

IPC分类号： H03H1126

CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254 ,  H03K5/133 ,  H03K2005/00091 ,  H03L7/0814

摘要： A delay time controlling circuit in a semiconductor memory device and method thereof for controlling a delay time preferably comprise a controller, a fuse unit having selectable fuse elements, a multiplexer, and a programmable variable delay circuit. With the multiplexer selecting the output of the controller, the controller generates a sequence of differing digital delay control signals to the programmable variable delay circuit in order to provide a plurality of unique delays in an output signal. When a desired time delay is monitored in the output signal, a programming signal is generated, which causes the specific digital control signal to be permanently programmed into the fuse unit via selective cutting of fuse elements. The multiplexer is then toggled via a selector fuse element to permanently select the output of the fuse unit as a control value source for the variable delay circuit.

公开(公告)号：US06580304B1

公开(公告)日：2003-06-17

申请号：US10109016

申请日：2002-03-28

申请人： Stephen Andrew Rieven

发明人： Stephen Andrew Rieven

IPC分类号： H03H1126

CPC分类号： H03H11/26

摘要： A precision signal delay apparatus and method for introducing time delay to a signal. Precision delay is introduced by a pair of delay locked loops (DLLs) connected in series each with selectable delay (i.e., a Vernier-type circuit). Nonuniformity in the precision delay is compensated with a delay compensation circuit. The apparatus and method may be used for phase shifting, data delay, precision pulse width modulation, and precision time windowing.

摘要翻译： 一种用于将时间延迟引入信号的精密信号延迟装置和方法。 通过一对以可选择的延迟串联连接的延迟锁定环（DLL）引入精确延迟（即，游标型电路）。 精度延迟的不均匀性由延迟补偿电路补偿。 该装置和方法可用于相移，数据延迟，精确脉冲宽度调制和精确时间窗口化。

公开(公告)号：US06573777B2

公开(公告)日：2003-06-03

申请号：US09893870

申请日：2001-06-29

申请人： Martin Saint-Laurent ,  Haytham Samarchi

发明人： Martin Saint-Laurent ,  Haytham Samarchi

IPC分类号： H03H1126

CPC分类号： H03H11/265 ,  H03K5/133 ,  H03K2005/00065 ,  H03K2005/00221

摘要： A clock distribution network is provided which includes variable-delay element. The variable-delay element consists of an inverter and a digitally adjustable resistor. The digitally adjustable resistor includes a plurality of transistors provided in plurality of rows and a plurality of columns. The variable-delay element functions logically equivalent to the inverter in which the delay is varied in accordance with the variance in resistance of the digitally adjustable resistor.

摘要翻译： 提供了包括可变延迟元件的时钟分配网络。 可变延迟元件由反相器和数字可调电阻组成。 数字可调电阻器包括设置在多行和多列中的多个晶体管。 可变延迟元件在逻辑上等效于延迟根据数字可调电阻器的电阻变化而变化的逆变器。

公开(公告)号：US06570427B2

公开(公告)日：2003-05-27

申请号：US09943668

申请日：2001-08-31

申请人： John S. Prentice

发明人： John S. Prentice

IPC分类号： H03H1126

CPC分类号： H03G1/0023 ,  H01L2924/0002 ,  H01L2924/00

摘要： A variable transconductance amplifier including a variable attenuator stage coupled to a transconductance stage. The variable attenuator includes first and second differential to single-ended transconductance stages, each biased by a current device. The variable attenuator receives a differential input voltage signal and develops a current signal. At least one reactive element is coupled between the pair of differential to single-ended transconductance stages. The transconductance stage includes first and second differential pairs each having first and second control terminals and first and second output terminals. The first and second differential pairs are coupled to the first and second differential to single-ended transconductance stages, respectively, of the variable attenuator. The output terminals of the first and second differential pair are cross-coupled to develop a differential output current signal. The stages include electronically controllable current devices so that the overall transconductance decreases when the input signal increases without distorting the output signal.

摘要翻译： 一种可变跨导放大器，包括耦合到跨导级的可变衰减器级。 可变衰减器包括第一和第二差分至单端跨导级，每一级由当前器件偏置。 可变衰减器接收差分输入电压信号并产生电流信号。 至少一个电抗元件耦合在该对差分至单端跨导级之间。 跨导级包括第一和第二差分对，每个具有第一和第二控制端以及第一和第二输出端。 第一和第二差分对分别耦合到可变衰减器的第一和第二差分至单端跨导级。 第一和第二差分对的输出端交叉耦合以形成差分输出电流信号。 这些级包括电子可控电流器件，使得当输入信号增加而不使输出信号失真时，整个跨导减小。

公开(公告)号：US06518811B1

公开(公告)日：2003-02-11

申请号：US09752367

申请日：2000-12-29

申请人： Rudolph B. Klecka, III

发明人： Rudolph B. Klecka, III

IPC分类号： H03H1126

CPC分类号： H04J3/0688 ,  H03H17/08 ,  H04J3/0691

摘要： A phase adjustment circuit has a signal path having a plurality of phase adjustment elements coupled together. Each of the phase adjustment elements of the plurality has a first path and a second path. The second path of each of the phase adjustment elements of the plurality adds a smaller amount of phase adjustment to the signal path than the first path of each of the phase adjustment elements of the plurality. The amount of phase adjustment added by each of the phase adjustment elements of the plurality is cumulative. The phase adjustment circuit also has a selection circuit coupled to each of the phase adjustment elements of the plurality to provide selection of either the first path or the second path of each of the phase adjustment elements of the plurality.

摘要翻译： 相位调整电路具有连接在一起的多个相位调整元件的信号路径。 多个相位调整元件中的每一个具有第一路径和第二路径。 多个相位调整元件的第二路径与多个相位调整元件的每一个的第一路径相比，对信号路径增加较少量的相位调整。 由多个相位调整元件相加的相位调整量是累积的。 相位调整电路还具有耦合到多个相位调整元件中的每一个的选择电路，以提供多个相位调整元件中的每一个的第一路径或第二路径的选择。

公开(公告)号：US06504413B1

公开(公告)日：2003-01-07

申请号：US09813572

申请日：2001-03-21

申请人： Colin Davidson

发明人： Colin Davidson

IPC分类号： H03H1126

CPC分类号： H03K17/164 ,  H03K19/01707

摘要： The present invention is directed to a buffer improvement for higher speed operation. A buffer may include at least two buffer stages, which may include a first buffer stage and a second buffer stage. A voltage conversion circuit is disposed between the first buffer stage and the second buffer stage. The voltage conversion circuit is suitable for acting as a delay between the first buffer stage and the second buffer stage. Additionally, the first buffer stage may be driven directly, thereby increasing buffer speed.

摘要翻译： 本发明涉及用于更高速度操作的缓冲器改进。 缓冲器可以包括至少两个缓冲级，其可以包括第一缓冲级和第二缓冲级。 电压转换电路设置在第一缓冲级和第二缓冲级之间。 电压转换电路适合用作第一缓冲级和第二缓冲级之间的延迟。 此外，可以直接驱动第一缓冲级，从而增加缓冲器速度。