公开(公告)号：US20100157035A1

公开(公告)日：2010-06-24

申请号：US12622373

申请日：2009-11-19

Applicant: Matthew Purcell ,  Graeme Storm ,  Derek Tolmie ,  Mhamed El Hachim ,  Laurent Simony ,  Min Qu

Inventor： Matthew Purcell ,  Graeme Storm ,  Derek Tolmie ,  Mhamed El Hachim ,  Laurent Simony ,  Min Qu

IPC: H04N7/18 ,  H04N5/335 ,  G06G7/18

CPC classification number: H04N5/3355 ,  H04N5/3577

Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.

Abstract translation: 图像传感器具有包括允许比较器电路执行相关双重采样的第一和第二电容器的每列ADC布置。 电容器分别连续地连接到模拟像素信号和斜坡信号，而不使用保持操作。 比较器电路包括差分输入端，连接到两个电容器的结，并被参考信号偏置。 参考信号优选地从参考电压采样和保持。 使用差分输入作为比较器的第一级，当大像素阵列以低对比度的场景成像时，可以解决地电压反弹引起的问题。 差分输入级的连接允许斜坡信号看到恒定的电容性负载，从而减少称为污迹的图像伪影。

公开(公告)号：US07725758B2

公开(公告)日：2010-05-25

申请号：US11641607

申请日：2006-12-18

Applicant: Jean-François Link ,  Dragos Davidescu ,  Sandrine Lendre

Inventor： Jean-François Link ,  Dragos Davidescu ,  Sandrine Lendre

IPC: G06F1/14 ,  G06F1/00 ,  G04F10/00

CPC classification number: G06F1/14

Abstract: A multifunctional timer/event counter device includes at least one counter controlled by a clock signal, and a control register including at least one binary number that will at least define a behavior of the counter. The device also includes a function module including at least one synchronization signal reception input and a reception input for at least one function control signal, the function module being capable of modifying the binary number as a function of at least the synchronization signal and the function control signal.

Abstract translation: 多功能计时器/事件计数器装置包括至少一个由时钟信号控制的计数器，以及控制寄存器，其包括将至少定义计数器的行为的至少一个二进制数。 该装置还包括功能模块，该功能模块包括用于至少一个功能控制信号的至少一个同步信号接收输入和接收输入，该功能模块能够修改作为至少该同步信号和功能控制的功能的二进制数 信号。

公开(公告)号：US07724735B2

公开(公告)日：2010-05-25

申请号：US11805856

申请日：2007-05-24

Applicant: Riccardo Locatelli ,  Marcello Coppola ,  Giuseppe Maruccia ,  Lorenzo Pieralisi

Inventor： Riccardo Locatelli ,  Marcello Coppola ,  Giuseppe Maruccia ,  Lorenzo Pieralisi

IPC: H04L12/56 ,  H04J1/16

CPC classification number: H04L47/39 ,  H04L47/2416 ,  H04L47/2433 ,  H04L49/254 ,  H04L2012/5679

Abstract: A bandwidth allocator to allocate in real time shared resources of a network on-chip is disclosed. The bandwidth allocator routes data packets between elements of the network in response to requests to access the shared resources. The bandwidth allocator could include a plurality of network interfaces to process the data packets to be routed within the network and a plurality of routers for routing the data packets through the network. A processor, distributed within the routers, controls the routers and the transmission of each data of the data packets through the routers to provide a bandwidth for each data flow. The network interfaces is adapted to fill a header field of each data packet with header field information depending on a requested bandwidth. The processor controls the transmission of the data packets through the routers as a function of the value of the header field information of each data packet.

Abstract translation: 公开了实时分配片上网络的共享资源的带宽分配器。 带宽分配器响应于访问共享资源的请求，在网络的元素之间路由数据分组。 带宽分配器可以包括多个网络接口来处理要在网络内路由的数据分组，以及用于通过网络路由数据分组的多个路由器。 分布在路由器内的处理器通过路由器控制路由器和数据包的每个数据的传输，为每个数据流提供带宽。 网络接口适于根据所请求的带宽填充每个数据分组的报头字段与报头字段信息。 处理器根据每个数据包的报头字段信息的值来控制数据包通过路由器的传输。

公开(公告)号：US07705760B2

公开(公告)日：2010-04-27

申请号：US12015093

申请日：2008-01-16

Applicant: Loïc Joet

Inventor： Loïc Joet

IPC: H03M1/12

CPC classification number: H04B1/16

Abstract: The invention relates to a method for the filtering and analog/digital conversion of an incoming analog signal including an analog filtering of the incoming analog signal so as to filter the frequency components located outside a desired frequency band, and a conversion of the filtered analog signal to a digital signal. The digital signal is reformatted in a form that is substantially similar, at least in the desired frequency band, to the form of the incoming analog signal. A final digital filtering of the reformatted digital signal is performed so as to filter the frequency components located outside the desired frequency band.

Abstract translation: 本发明涉及一种用于滤波和模拟/数字转换输入模拟信号的方法，包括输入模拟信号的模拟滤波，以便对位于期望频带之外的频率分量进行滤波，以及滤波模拟信号的转换 到数字信号。 数字信号以至少在所需频带中基本相似的形式重新格式化为输入模拟信号的形式。 执行重新格式化的数字信号的最终数字滤波，以便对位于期望频带之外的频率分量进行滤波。

公开(公告)号：US07696844B2

公开(公告)日：2010-04-13

申请号：US11829549

申请日：2007-07-27

Applicant: Andreia Cathelin ,  Stéphane Razafimandimby ,  Andreas Kaiser

Inventor： Andreia Cathelin ,  Stéphane Razafimandimby ,  Andreas Kaiser

IPC: H03H9/54

CPC classification number: H03H9/0095 ,  H03H2009/02204

Abstract: A filtering circuit based on a lattice structure comprising a first and a second input and a first and second output. The circuit further comprises two series impedance and two parallel impedance which each comprises an acoustic resonator associated with two inductive and capacitive components which can be adjusted by a first control value. The second and fourth impedance comprise each an acoustic resonator associated to two inductive and capacitive components which are adjustable by means of a second control value. A control circuit generates the two control values which simultaneously comprise a common mode potential and a differential mode potential which allows the emergence of first and second pass bands which are usable for realizing two different bandpass filters.

Abstract translation: 一种基于包括第一和第二输入以及第一和第二输出的晶格结构的滤波电路。 电路还包括两个串联阻抗和两个并联阻抗，每个阻抗均包括与两个电感和电容部件相关联的声谐振器，这两个电感和电容部件可以通过第一控制值进行调节。 第二和第四阻抗包括每个与谐振器相关联的声谐振器，两个电感和电容元件可通过第二控制值进行调节。 控制电路产生同时包括共模电位和差模电位的两个控制值，允许出现可用于实现两个不同带通滤波器的第一和第二通带。

公开(公告)号：US07680069B2

公开(公告)日：2010-03-16

申请号：US11484880

申请日：2006-07-11

Applicant: Anca-Marina Ianos ,  Paolo Pesenti

Inventor： Anca-Marina Ianos ,  Paolo Pesenti

IPC: H04B7/005

CPC classification number: H04B14/04 ,  H04L7/0008 ,  H04M1/6066

Abstract: An interface device having a first and second data terminal configured for the communication of data in duplex mode, with one of the first and second data terminals always assigned to each direction of the communication, the first and second data terminals configurable during operation such that, in a first mode of operation, the first data terminal is configured to send but not to receive data and the second data terminal is configured to receive but not send data, while in a second mode of operation the first data terminal is configured to receive but not to send data and the second data terminal is configured to send but not to receive data.

Abstract translation: 一种具有第一和第二数据终端的接口设备，其被配置用于以双工模式通信数据，所述第一和第二数据终端中的一个总是被分配给通信的每个方向，所述第一和第二数据终端在操作期间可配置， 在第一操作模式中，第一数据终端被配置为发送但不接收数据，并且第二数据终端被配置为接收但不发送数据，而在第二操作模式中，第一数据终端被配置为接收但不 不发送数据，第二个数据终端配置为发送但不接收数据。

公开(公告)号：US07673095B2

公开(公告)日：2010-03-02

申请号：US11016325

申请日：2004-12-17

Applicant: Alain Artieri

Inventor： Alain Artieri

IPC: G06F13/00

CPC classification number: G11C11/419 ,  G06F5/10

Abstract: A FIFO memory with a frequency f and a size of M n-bit words, to successively store n-bit words received serially at an input and give said words serially at an output in the order in which they are stored, comprises a basic memory with a frequency f/2, capable of simultaneously storing two n-bit words successively received at the input of the FIFO memory. The memory also comprises a storage circuit to store either one n-bit word received at the input of the FIFO memory or simultaneously two n-bit words produced by the basic memory and to produce, at the output OUT of the FIFO memory, one of the words that said storage circuit stores.

Abstract translation: 具有频率f和M个n位字的大小的FIFO存储器，以连续地存储在输入处串行接收的n位字，并以其存储顺序在输出处串行地给出所述字，包括基本存储器 具有频率f / 2，能够同时存储在FIFO存储器的输入端连续接收的两个n位字。 存储器还包括存储电路，用于存储在FIFO存储器的输入处接收到的一个n位字，或者同时存储由基本存储器产生的两个n位字，并且在FIFO存储器的输出OUT处产生 所述存储电路存储的字。

公开(公告)号：US20100045390A1

公开(公告)日：2010-02-25

申请号：US12543162

申请日：2009-08-18

Applicant: Sebastien BARASINSKI

Inventor： Sebastien BARASINSKI

IPC: H03K3/03 ,  G01R31/02

CPC classification number: G01R31/2884 ,  H01L22/34 ,  H03K3/0315 ,  H03K5/133 ,  H03K2005/00156

Abstract: An integrated circuit may include an inverter which may include a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in parallel with the first transistor. An input of the inverter may be capable of receiving an oscillating input signal, and which may include an output of the inverter, which is connected to a capacitive device capable of being charged and discharged depending on the state of the first and second transistors being on or off. The inverter may be capable of delivering an oscillating output signal at its output. The integrated circuit may include a selector for transmitting the oscillating output signal and for masking the charging and/or discharging of the capacitive device.

Abstract translation: 集成电路可以包括可以包括与第一晶体管并联连接的第一导电类型的第一晶体管和第二导电类型的第二晶体管的反相器。 反相器的输入端可以能够接收振荡输入信号，并且其可以包括反相器的输出，该反相器的输出根据第一和第二晶体管的状态被连接到能够被充放电的电容器件 或关闭。 逆变器可以在其输出端输出振荡输出信号。 集成电路可以包括用于发送振荡输出信号并用于屏蔽电容性装置的充电和/或放电的选择器。

公开(公告)号：US20100045342A1

公开(公告)日：2010-02-25

申请号：US12543395

申请日：2009-08-18

Applicant: Sylvain Majcherczak

Inventor： Sylvain Majcherczak

IPC: H03K19/0175 ,  H03L5/00

CPC classification number: H03K19/018514

Abstract: A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit.

Abstract translation: 包括并联的两对分支的电压电平转换器电路，每对包括低阻分支，其中可以激活或去激活低阻分支。 可能的应用是来自集成电路的数据的电压电平切换。

公开(公告)号：US07668449B2

公开(公告)日：2010-02-23

申请号：US11534141

申请日：2006-09-21

Applicant: Eric Saugier ,  Jean-Luc Diot ,  Fabrice Mee

Inventor： Eric Saugier ,  Jean-Luc Diot ,  Fabrice Mee

IPC: G03B17/00

CPC classification number: G02B7/09 ,  G02B7/02

Abstract: A barrel for an electrically-controllable variable focal length lens in a button-battery type housing includes a hollow isolating cylindrical tube with an inner diameter substantially equal to that of the lens housing, with one or bumps extending radially towards the inside of the tube and forming bearing surfaces for the lens periphery in a same radial plane. First metallizations extend on at least one of the bearing surfaces and therefrom into first channels formed in the internal wall of the tube towards at least one end of the tube, and second metallizations, each of which forms a contact area on the internal surface of the tube to bear against the lateral surface of the lens and extends towards at least one end of the cylinder.

Abstract translation: 用于钮扣电池型壳体中的电控可变焦距透镜的镜筒包括具有与透镜壳体的内径基本相等的内径的中空隔离圆柱形管，其中一个或凸块径向朝向管的内部延伸， 在相同的径向平面中形成用于透镜周边的支承表面。 第一金属化在至少一个轴承表面上延伸并从而延伸到形成在管的内壁中的第一通道朝向管的至少一个端部，并且第二金属化部分形成在内表面上的接触区域 管抵靠透镜的侧表面并朝向气缸的至少一端延伸。