公开(公告)号：US20190311976A1

公开(公告)日：2019-10-10

申请号：US16370193

申请日：2019-03-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Francesco SALAMONE ,  Cristiano Gianluca STELLA

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.

公开(公告)号：US20190310860A1

公开(公告)日：2019-10-10

申请号：US16375695

申请日：2019-04-04

Applicant: STMicroelectronics S.r.l.

Inventor： Pasquale Vastano ,  Amedeo Veneroso

IPC: G06F9/4401 ,  H04L9/08

Abstract: A method for managing storage of an operating system in an integrated circuit card, includes: subdividing an operating system into a plurality of operating system components; associating one or more operating system components of the plurality of operating system components to a descriptor indicating a version of the one or more operating system components; downloading the one or more operating system components to a memory of the integrated circuit card, wherein the downloading includes verifying if an operating system component stored in the integrated circuit card is a same version of the one or more operating system components being downloaded; based on the verifying, storing the one or more operating system components in the card if the version is different; and based on the verifying discarding the one or more operating system components from the download operation if the version is the same.

公开(公告)号：US20190310103A1

公开(公告)日：2019-10-10

申请号：US16433874

申请日：2019-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Paolo Rivolta ,  Andrea Labombarda ,  Alberto Zancanato

IPC: G01C22/00

Abstract: An activity tracking device, such as a step-counting device includes an interface configured to receive one or more acceleration signals and signal processing circuitry. The signal processing circuitry generates an indication of condition of an accelerometer, such as a body position of the accelerometer, based on one or more accelerometer signals, generates an event signal, such as an event flag, based on one or more accelerometer signals and the indication of the condition of the accelerometer, and generates an activity signal, such as step flag based on the event signal, the indication of the condition of the accelerometer and one or more acceleration signals. The signal processing circuitry may generate a noise signal based on one or more acceleration signals and generate the activity signal based on the noise signal.

公开(公告)号：US10439569B2

公开(公告)日：2019-10-08

申请号：US15984942

申请日：2018-05-21

Applicant: STMicroelectronics S.r.l.

Inventor： Stefano Ramorini ,  Alberto Cattani ,  Germano Nicollini ,  Alessandro Gasparini

IPC: H03F3/21 ,  H03F3/217 ,  H03F3/45 ,  G01R1/30 ,  G01R19/00

Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.

公开(公告)号：US20190305775A1

公开(公告)日：2019-10-03

申请号：US16371919

申请日：2019-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro PARISI ,  Nunzio GRECO ,  Nunzio SPINA ,  Egidio RAGONESE ,  Giuseppe PALMISANO

IPC: H03K17/722 ,  H03B5/06

Abstract: An oscillator is coupled to a first side of a galvanic barrier for supplying thereto an electric supply signal. The oscillator is configured to be alternatively turned on and off as a function of a PWM drive signal applied thereto. A receiver circuit coupled to the galvanic barrier receives therefrom a PWM power control signal. A signal reconstruction circuit coupled between the receiver circuit block and the oscillator provides to the oscillator a PWM drive signal reconstructed from the PWM power control signal. The signal reconstruction circuit includes a PLL circuit coupled to the receiver circuit block and configured to lock to the PWM control signal from the receiver circuit block. A PLL loop within the PLL circuit is sensitive to the PWM drive signal applied to the oscillator. The PLL loop is configured to be opened as a result of the power supply oscillator being turned off.

公开(公告)号：US20190296004A1

公开(公告)日：2019-09-26

申请号：US16353658

申请日：2019-03-14

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics S.r.l.

Inventor： Aurelie Arnaud ,  Andrea Brischetto

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/16 ,  H02H9/04

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

公开(公告)号：US20190295934A1

公开(公告)日：2019-09-26

申请号：US15934783

申请日：2018-03-23

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Paolo CREMA

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

Abstract: The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.

公开(公告)号：US20190292045A1

公开(公告)日：2019-09-26

申请号：US16442199

申请日：2019-06-14

Applicant: STMicroelectronics S.r.l.

Inventor： Alberto Pagani ,  Alessandro Motta

IPC: B81C1/00 ,  G01L9/00 ,  B81B3/00 ,  B81B7/00

Abstract: A method for making an integrated micro-electromechanical device includes forming a first body of semiconductor material having a first face and a second face opposite the first face. The first body includes a buried cavity forming a diaphragm delimited between the buried cavity and the first face. The diaphragm is monolithic with the first body. The method further includes forming at least one first magnetic via extending between the second face and the buried cavity of the first body, forming a first magnetic region extending over the first face of the first body, and forming a first coil extending over the second face of the first body and being magnetically coupled to the first magnetic via.

公开(公告)号：US10422968B2

公开(公告)日：2019-09-24

申请号：US15985860

申请日：2018-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： Antonio Fincato ,  Luca Maggi

IPC: G02B6/42 ,  H01L23/58 ,  G02B6/30 ,  G02B6/28 ,  G02B6/12

Abstract: A semiconductor chip provides an optical medium for light propagation. The semiconductor chip includes a chip surface with an outer perimeter and a cavity in the chip surface. The cavity includes a peripheral wall and a bottom surface surrounded by the peripheral wall, the bottom surface adiabatically couplable to an optical waveguide. The cavity is located at an area of the chip surface spaced from the outer perimeter thereof.

公开(公告)号：US20190287880A1

公开(公告)日：2019-09-19

申请号：US15925420

申请日：2018-03-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Cristina SOMMA ,  Fulvio Vittorio FONTANA

IPC: H01L23/495

Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.