公开(公告)号：US20230290770A1

公开(公告)日：2023-09-14

申请号：US18052158

申请日：2022-11-02

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics S.r.l.

Inventor： Aurelie Arnaud ,  Andrea Brischetto

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/861 ,  H02H9/04

CPC classification number: H01L27/0248 ,  H01L29/16 ,  H01L29/861 ,  H02H9/046 ,  H01L27/0255

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

公开(公告)号：US20190296004A1

公开(公告)日：2019-09-26

申请号：US16353658

申请日：2019-03-14

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics S.r.l.

Inventor： Aurelie Arnaud ,  Andrea Brischetto

IPC: H01L27/02 ,  H01L29/861 ,  H01L29/16 ,  H02H9/04

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

公开(公告)号：US11515301B2

公开(公告)日：2022-11-29

申请号：US16353658

申请日：2019-03-14

Applicant: STMicroelectronics (Tours) SAS ,  STMicroelectronics S.r.l.

Inventor： Aurelie Arnaud ,  Andrea Brischetto

IPC: H01L27/02 ,  H01L29/16 ,  H01L29/861 ,  H02H9/04

Abstract: An ESD protection circuit includes a terminal connected to the cathode of a first diode and to the anode of a second diode, where the cathode of the second diode is not made of epitaxial silicon.

公开(公告)号：US20150221628A1

公开(公告)日：2015-08-06

申请号：US14171931

申请日：2014-02-04

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/02 ,  H01L27/08

CPC classification number: H01L27/0248 ,  H01L27/0259 ,  H01L27/0814

Abstract: An overvoltage protection device including: a doped substrate of a first conductivity type having a first doping level, coated with a doped epitaxial layer of the second conductivity type having a second doping level; a first doped buried region of the second conductivity type having a third doping level greater than the second level, located at the interface between the substrate and the epitaxial layer in a first portion of the device; and a second doped buried region of the first conductivity type having a fourth doping level greater than the first level, located at the interface between the substrate and the epitaxial layer in a second portion of the device.

Abstract translation: 一种过电压保护装置，包括：具有第一掺杂水平的第一导电类型的掺杂衬底，涂覆有具有第二掺杂水平的第二导电类型的掺杂外延层; 所述第二导电类型的第一掺杂掩埋区具有大于所述第二电平的第三掺杂水平，位于所述器件的第一部分中的所述衬底和所述外延层之间的界面处; 以及第一导电类型的第二掺杂掩埋区，其具有大于所述第一电平的第四掺杂水平，位于所述器件的第二部分中的所述衬底和所述外延层之间的界面处。

公开(公告)号：US10529703B2

公开(公告)日：2020-01-07

申请号：US15436998

申请日：2017-02-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie Arnaud

IPC: H01L23/60 ,  H01L27/02 ,  H01L21/265 ,  H01L21/324 ,  H01L27/08 ,  H01L29/06 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66 ,  H02H9/04

Abstract: An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity type; a first heavily-doped buried semiconductor layer of a second conductivity type; a first lightly-doped semiconductor layer of the second conductivity type; and a second heavily-doped layer of the first conductivity type. The device further includes, located between first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third doped layer of the first conductivity type having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and the third layer, a diode having a reverse punchthrough operation.

公开(公告)号：US12230628B2

公开(公告)日：2025-02-18

申请号：US18053722

申请日：2022-11-08

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/07 ,  H01L27/02 ,  H01L21/265 ,  H01L21/266

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

公开(公告)号：US20180026027A1

公开(公告)日：2018-01-25

申请号：US15436998

申请日：2017-02-20

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/36 ,  H01L29/167 ,  H01L27/08 ,  H01L21/265 ,  H01L21/324 ,  H02H9/04 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L21/26513 ,  H01L21/324 ,  H01L27/0814 ,  H01L29/0684 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66113 ,  H01L29/861 ,  H02H9/044

Abstract: An electrostatic discharge protection device includes the following successive structures: a very heavily-doped semiconductor substrate of a first conductivity type; a first heavily-doped buried semiconductor layer of a second conductivity type; a first lightly-doped semiconductor layer of the second conductivity type; and a second heavily-doped layer of the first conductivity type. The device further includes, located between first heavily-doped buried semiconductor layer and the first lightly-doped semiconductor layer, a third doped layer of the first conductivity type having a thickness and a dopant atom concentration configured to form, at a junction of the first lightly-doped semiconductor layer and the third layer, a diode having a reverse punchthrough operation.

公开(公告)号：US09257420B2

公开(公告)日：2016-02-09

申请号：US14171931

申请日：2014-02-04

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie Arnaud

IPC: H01L29/02 ,  H01L27/02 ,  H01L27/08

CPC classification number: H01L27/0248 ,  H01L27/0259 ,  H01L27/0814

Abstract: An overvoltage protection device including: a doped substrate of a first conductivity type having a first doping level, coated with a doped epitaxial layer of the second conductivity type having a second doping level; a first doped buried region of the second conductivity type having a third doping level greater than the second level, located at the interface between the substrate and the epitaxial layer in a first portion of the device; and a second doped buried region of the first conductivity type having a fourth doping level greater than the first level, located at the interface between the substrate and the epitaxial layer in a second portion of the device.

Abstract translation: 一种过电压保护装置，包括：具有第一掺杂水平的第一导电类型的掺杂衬底，涂覆有具有第二掺杂水平的第二导电类型的掺杂外延层; 所述第二导电类型的第一掺杂掩埋区具有大于所述第二电平的第三掺杂水平，位于所述器件的第一部分中的所述衬底和所述外延层之间的界面处; 以及第一导电类型的第二掺杂掩埋区，其具有大于所述第一电平的第四掺杂水平，位于所述器件的第二部分中的所述衬底和所述外延层之间的界面处。

公开(公告)号：US11532616B2

公开(公告)日：2022-12-20

申请号：US16709753

申请日：2019-12-10

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Aurelie Arnaud

IPC: H01L27/07 ,  H01L27/02 ,  H01L21/265 ,  H01L21/266

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

公开(公告)号：US11362084B2

公开(公告)日：2022-06-14

申请号：US17143703

申请日：2021-01-07

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie Arnaud ,  Severine Lebrette

IPC: H01L27/00 ,  H01L27/02 ,  H01L21/22 ,  H01L29/66 ,  H01L29/866

Abstract: ESD protection devices and methods are provided. In at least one embodiment, a device includes a first stack that forms a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type located therein. The first area is flush with a surface of the substrate. A second stack forms a diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of the second conductivity type having a second region of the first conductivity type located therein. The second area is flush, opposite the first stack, with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, on and in contact with the second stack.