公开(公告)号：US07336718B2

公开(公告)日：2008-02-26

申请号：US10735251

申请日：2003-12-12

Applicant: Helder Da-Silva-Valente ,  Frederic Lehmann

Inventor： Helder Da-Silva-Valente ,  Frederic Lehmann

IPC: H04L23/02 ,  H03M13/03

CPC classification number: H04L25/067 ,  H04L27/38

Abstract: A method decodes a noisy signal from the coordinates of a point in a point constellation, each point associated with a digital data item of a determined number of bits, consisting of determining components of a received point; determining a reference point corresponding to the constellation point closest to the received point; determining at least one concurrent point corresponding to the constellation point closest to the reference point, having a bit of determined rank opposite to the bit of determined rank of the reference data; and determining, at least for the bit of the reference digital data at said determined rank, a precision data item based the received, reference, and concurrent points, in which the determination of the bits of the concurrent point is performed based on the values of some of the bits of the reference digital data and on said rank.

Abstract translation: 一种方法从点星座中的点的坐标解码噪声信号，每个点与确定的位数的数字数据项相关联，包括确定接收点的分量; 确定对应于最接近接收点的星座点的参考点; 确定对应于最接近所述参考点的星座点的至少一个并发点，其具有与所述参考数据的确定秩的位相反的确定秩的比特; 以及至少针对所述确定的等级的所述参考数字数据的比特，基于所接收的，参考的和并发的点来确定精确数据项，其中根据 参考数字数据的一些位和所述等级。

公开(公告)号：US07333118B2

公开(公告)日：2008-02-19

申请号：US10988981

申请日：2004-11-12

Applicant: Yan Meroth

Inventor： Yan Meroth

IPC: G09G5/02

CPC classification number: G09G5/02 ,  G09G2340/0428 ,  H04N1/644

Abstract: A method and a device for processing an image to be displayed with a reduced number n of color components are disclosed. The method comprises, for at least one of the color components, a reduction operation that is carried out by means of a dynamic round off dependent on the position (x, y) of the pixel to display. Thus, in a very simple way, image processing preventing the occurrence of artifacts, flickering or other flaws that the reduction of the number of colors would inevitably produce, can be realized.

Abstract translation: 公开了一种用于处理以减少n个颜色分量显示的图像的方法和装置。 对于至少一个颜色分量，该方法包括通过取决于要显示的像素的位置（x，y）的动态舍入来执行的缩小操作。 因此，以非常简单的方式，可以实现防止不可避免地产生颜色数量的减少的伪像，闪烁或其他缺陷的发生的图像处理。

公开(公告)号：US07327005B2

公开(公告)日：2008-02-05

申请号：US10478178

申请日：2002-05-17

Applicant: Remi Brechignac ,  Juan Exposito

Inventor： Remi Brechignac ,  Juan Exposito

IPC: H01L31/0203

CPC classification number: H01L23/552 ,  G01D5/264 ,  G01D11/245 ,  H01L24/48 ,  H01L24/49 ,  H01L27/14618 ,  H01L27/14625 ,  H01L31/0203 ,  H01L31/02325 ,  H01L33/58 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/12043 ,  H01L2924/15153 ,  H01L2924/15162 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/16151 ,  H01L2924/16195 ,  H01L2924/3025 ,  H04N5/2257 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An optical semiconductor module including an optical semiconductor component that has a front face including an optical sensor. Encapsulation, defining a cavity in which the optical component is disposed, includes external electrical connections for the optical semiconductor component, and includes a window allowing light to pass through it toward the optical sensor. An optical lens (17) is disposed in the cavity (6) between the optical sensor (10) and the window (5). A support structure (18) supports the optical lens. This optical semiconductor module may also include a shield (24).

Abstract translation: 一种光学半导体模块，包括具有包括光学传感器的正面的光学半导体部件。 限定其中设置有光学部件的空腔的封装包括用于光学半导体部件的外部电连接，并且包括允许光通过光学传感器的窗口。 光学透镜（17）设置在光学传感器（10）和窗口（5）之间的空腔（6）中。 支撑结构（18）支撑光学透镜。 该光学半导体模块还可以包括屏蔽（24）。

公开(公告)号：US20080024509A1

公开(公告)日：2008-01-31

申请号：US11766460

申请日：2007-06-21

Applicant: Patrice Couvert ,  Anthony Philippe

Inventor： Patrice Couvert ,  Anthony Philippe

IPC: G06F12/00

CPC classification number: G06T1/60 ,  G06F9/345 ,  G06F9/3552 ,  H04N19/433 ,  H04N19/51

Abstract: A system comprises a memory storing data at addresses associated with pixels in images, each address being linked by a function to coordinates of a pixel in an ordered image reference frame, a device for processing the data associated with the pixels, where a pixel being processed is referenced by an associated vector relative to a reference pixel, and an interface device providing data to the processing device. A data request indicates a vector associated with a pixel being processed. The coordinates of the reference pixel are determined by applying the function to an address associated with the reference pixel. Next the coordinates of the pixel being processed are obtained based on the coordinates of the reference pixel and on the vector. Then the address of the data associated with the pixel being processed is determined by applying the inverse function of the function to the coordinates of the pixel being processed.

Abstract translation: 一种系统包括存储与图像中的像素相关联的地址的数据的存储器，每个地址通过功能与有序图像参考帧中的像素的坐标相关联，用于处理与像素相关联的数据的设备，其中处理像素 由关联的向量相对于参考像素引用，以及向处理设备提供数据的接口设备。 数据请求指示与正在处理的像素相关联的向量。 参考像素的坐标通过将函数应用于与参考像素相关联的地址来确定。 接下来，基于参考像素的坐标和向量来获得正在处理的像素的坐标。 然后，通过将函数的反函数应用于正在处理的像素的坐标来确定与正在处理的像素相关联的数据的地址。

公开(公告)号：US07319758B2

公开(公告)日：2008-01-15

申请号：US09727300

申请日：2000-11-30

Applicant: Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

Inventor： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

IPC: H04L9/00 ,  G06F11/30 ,  G06F1/04 ,  G06F3/00

CPC classification number: H04L9/0891 ,  H04L9/0631 ,  H04L2209/04

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Abstract translation: 在包括双向总线的电子部件中，数据元件通过该双向总线以时钟信号的速率在外围设备和中央处理单元之间行进，中央处理单元和至少一个外围设备都包括数据加密/解密单元。 每个数据加密/解密单元使用相同的秘密密钥。 秘密密钥是从与时钟信号同步的随机信号在每个小区中的每个时钟周期本地产生的，并且通过单向传输线应用于每个小区。

公开(公告)号：US20080007336A1

公开(公告)日：2008-01-10

申请号：US11774021

申请日：2007-07-06

Applicant: Didier BELOT ,  Jean-Baptiste Begueret ,  Yann Deval ,  Herve Lapuyade

Inventor： Didier BELOT ,  Jean-Baptiste Begueret ,  Yann Deval ,  Herve Lapuyade

IPC: H03F3/04

CPC classification number: H03D3/008 ,  H04B1/30

Abstract: A method is for reducing a DC component of an input signal transposed into baseband and being generated by a first frequency transposition stage starting from an initial signal and from a transposition signal. The method includes amplifying the transposed input signal in a first amplifier. The first amplifier receives at a DC offset compensation input, a compensation signal extracted from an output signal of a second amplifier subjected to a compensation of a offset DC voltage of the second amplifier. The method also included alternating between receiving at an input of the second amplifier, a first auxiliary signal from an auto-transposition of a transposition signal in a second frequency transposition stage and a second auxiliary signal from a transposition of the initial signal in the second frequency transposition stage with the transposition signal.

Abstract translation: 一种方法是减少转换成基带的输入信号的DC分量，并且由初始信号和转置信号开始由第一频率转置级产生。 该方法包括在第一放大器中放大转置的输入信号。 第一放大器在DC偏移补偿输入处接收从经过补偿第二放大器的偏移DC电压的第二放大器的输出信号提取的补偿信号。 该方法还包括在第二放大器的输入处接收来自第二频率转置级中的转置信号的自动转置的第一辅助信号和来自第二频率中的初始信号的转置的第二辅助信号之间的交替 转置阶段与转置信号。

公开(公告)号：US20080002474A1

公开(公告)日：2008-01-03

申请号：US11754707

申请日：2007-05-29

Applicant: Francesco La Rosa

Inventor： Francesco La Rosa

IPC: G11C11/34

CPC classification number: G11C16/0433 ,  H01L27/115

Abstract: The present invention relates to a method for programming or erasing memory cells that include a selection transistor connected to a floating-gate transistor. According to the method, a non-zero compensation voltage is applied to the gate of a transistor not involved in the programming or erasing process so as to increase a breakdown threshold of the transistor, and an inhibition voltage is applied to the gate or to a terminal of at least one floating-gate transistor connected to the transistor having its breakdown threshold increased to inhibit a phenomenon of soft programming or soft erase of the floating-gate transistor.

Abstract translation: 本发明涉及一种编程或擦除存储单元的方法，该存储单元包括连接到浮栅晶体管的选择晶体管。 根据该方法，将非零补偿电压施加到不参与编程或擦除处理的晶体管的栅极，以增加晶体管的击穿阈值，并且将抑制电压施加到栅极或栅极 连接到具有其击穿阈值的晶体管的至少一个浮栅晶体管的端子增加以抑制浮动栅极晶体管的软编程或软擦除现象。

公开(公告)号：US20070300015A1

公开(公告)日：2007-12-27

申请号：US11852937

申请日：2007-09-10

Applicant: Sebastien Zink ,  Paola Cavaleri ,  Bruno Leconte

Inventor： Sebastien Zink ,  Paola Cavaleri ,  Bruno Leconte

IPC: G06F12/00

CPC classification number: G11C8/12 ,  G11C8/04

Abstract: The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. The memory stores a most significant address allocated to the memory within an extended memory array wherein the memory is incorporated or intended to be incorporated. A master memory signal is generated based on the most significant address allocated to the memory. A central processing unit executes a command for reading the register and supplies the content of the register to the serial input/output of the memory only if the memory is the master memory within the extended memory array. The memory includes slave memories whose operation depends upon the read/write status of the master memory.

Abstract translation: 本发明涉及一种硅微芯片上的存储器，具有串行输入/输出，可在N位下寻址的集成存储器阵列，以及至少一个可读取的寄存器，在将寄存器读取到存储器之后。 存储器存储在扩展存储器阵列中分配给存储器的最重要的地址，其中存储器被并入或旨在被并入。 基于分配给存储器的最高有效地址产生主存储器信号。 中央处理单元执行用于读取寄存器的命令，并且仅当存储器是扩展存储器阵列内的主存储器时才将寄存器的内容提供给存储器的串行输入/输出。 存储器包括从存储器，其操作取决于主存储器的读/写状态。

公开(公告)号：US20070285355A1

公开(公告)日：2007-12-13

申请号：US11753189

申请日：2007-05-24

Applicant: Jerome Bourgoin ,  Gilles Troussel

Inventor： Jerome Bourgoin ,  Gilles Troussel

IPC: G09G3/28

CPC classification number: G09G3/296 ,  G09G3/293 ,  G09G2310/0248 ,  G09G2310/0275 ,  G09G2330/023

Abstract: The control of a plasma display panel, successively comprises, at least for all the cells of a current line having to switch state for the next line: a connection of a terminal of application of an intermediary supply voltage to output terminals of column control stages corresponding to the junction points of first and second switches between two terminals of application of a supply voltage, to perform a precharge or a predischarge of the screen cells; a disconnection of said output terminals from this intermediary voltage; and a connection of each output terminal to a first or to a second power supply voltage by the turning-on of the first or second switch of the corresponding stage, according to a luminance reference value, delayed with respect to the disconnection of the corresponding output terminal from the terminal of application of the intermediary voltage.

Abstract translation: 等离子体显示面板的控制至少对于具有下一行的开关状态的电流线的所有单元依次包括：将中间供电电压施加到对应于列控制级的输出端的端子的连接 到施加电源电压的两个端子之间的第一和第二开关的接点，以执行屏幕单元的预充电或预充电; 所述输出端子与该中间电压的断开; 以及根据相对于相应输出端断开延迟的亮度参考值，通过相应级的第一或第二开关的导通来将每个输出端子连接到第一或第二电源电压 终端从终端应用中介电压。

公开(公告)号：US20070284625A1

公开(公告)日：2007-12-13

申请号：US11761122

申请日：2007-06-11

Applicant: Jean-Francois Damlencourt ,  Yves Morand ,  Laurent Clavelier

Inventor： Jean-Francois Damlencourt ,  Yves Morand ,  Laurent Clavelier

IPC: H01L23/58

CPC classification number: H01L21/32105 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/3083 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates to a method for producing a microelectronic device including a plurality of Si1-yGey based semi-conducting zones (where 0

Abstract translation: 本公开涉及一种用于生产包括多个基于Si 1-y基于半导电区（其中0