公开(公告)号：US07319758B2

公开(公告)日：2008-01-15

申请号：US09727300

申请日：2000-11-30

申请人： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

发明人： Alain Pomet ,  Bernard Plessier ,  Laurent Sourgen

IPC分类号： H04L9/00 ,  G06F11/30 ,  G06F1/04 ,  G06F3/00

CPC分类号： H04L9/0891 ,  H04L9/0631 ,  H04L2209/04

摘要： In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

摘要翻译： 在包括双向总线的电子部件中，数据元件通过该双向总线以时钟信号的速率在外围设备和中央处理单元之间行进，中央处理单元和至少一个外围设备都包括数据加密/解密单元。 每个数据加密/解密单元使用相同的秘密密钥。 秘密密钥是从与时钟信号同步的随机信号在每个小区中的每个时钟周期本地产生的，并且通过单向传输线应用于每个小区。

公开(公告)号：US5619165A

公开(公告)日：1997-04-08

申请号：US417852

申请日：1995-04-06

申请人： Richard P. Fournel ,  Laurent Sourgen

发明人： Richard P. Fournel ,  Laurent Sourgen

IPC分类号： G01R19/165 ,  G06F1/28 ,  H03K17/22 ,  G05F1/00

CPC分类号： G01R19/16519

摘要： A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition.

摘要翻译： 用于低功率集成电路的电源电压监控电路，其中通过开关电容器链的电荷共享用于将电源电压耦合到动态感测节点。 动态感应节点驱动一个半锁定，在无报警状态下稳定。

公开(公告)号：US5099451A

公开(公告)日：1992-03-24

申请号：US272123

申请日：1988-11-16

申请人： Laurent Sourgen ,  Gilles Lisimaque ,  Jean Devin

发明人： Laurent Sourgen ,  Gilles Lisimaque ,  Jean Devin

IPC分类号： G11C14/00 ,  G11C11/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/005 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/06 ,  G11C16/10

摘要： To avoid differentiation, in manufacture, between the random-access memory cells and read-only memory cells of the same memory array, the memory cells are all made by the same technology. These memory cells employ essentially floating gate transistors. The random-access memory cells are programmed, in a stand way, by injecting or not electronic charges in the floating gates of the transistors. The read-only memory cells are put in a programmed or an unprogrammed state by the selective implantation of impurities or not in the conduction channels of the floating gate transistors of these memory cells. There is an improved concealment of the content, which is designed to remain concealed, of these memory cells, at the same time, the conditions for making prototypes to order are improved.

摘要翻译： 为了避免差异化，在制造中，在相同存储器阵列的随机存取存储器单元和只读存储器单元之间，存储单元都由相同的技术制成。 这些存储单元基本上采用浮置晶体管。 随机存取存储器单元以静态方式通过在晶体管的浮置栅极中注入或不注入电子来编程。 只读存储器单元通过选择性地注入杂质而不是在这些存储单元的浮置栅晶体管的导通通道中被置于编程状态或未编程状态。 改进了对这些存储器单元的隐藏内容的改进的隐藏，同时提高了制作原型的条件。

公开(公告)号：US5978915A

公开(公告)日：1999-11-02

申请号：US573942

申请日：1995-12-18

申请人： Mathieu Lisart ,  Laurent Sourgen

发明人： Mathieu Lisart ,  Laurent Sourgen

IPC分类号： G06F12/14 ,  G06F21/02 ,  G06K17/00 ,  G06F11/00 ,  G11C17/00

CPC分类号： G06F12/1425

摘要： The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives also addresses of the control bits of a control word assigned to a word to be protected. It can be shown that this mode of action provides greater security through the use of a decision table made in wired circuit form as well as greater flexibility through the programmable quality of the control words assigned to each memory word to be controlled.

摘要翻译： 通过创建接收要保护的指令字和/或数据字的地址的决定表来保护对集成电路的存储字的访问，并且还接收分配给一个字的控制字的控制位的地址 被保护。 可以看出，这种操作模式通过使用以有线电路形式制定的决策表以及通过分配给要控制的每个存储器字的控制字的可编程质量而具有更大的灵活性来提供更大的安全性。

公开(公告)号：US5440263A

公开(公告)日：1995-08-08

申请号：US53892

申请日：1993-04-27

申请人： Richard P. Fournel ,  Laurent Sourgen

发明人： Richard P. Fournel ,  Laurent Sourgen

IPC分类号： G01R19/165 ,  G06F1/28 ,  H03K17/22 ,  G05F1/00

CPC分类号： G01R19/16519

摘要： A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition. In this circuit, the state of the output gets switched over in the first phase if the voltage at the terminals of the capacitor at the start of this stage (this voltage being equal to a fraction of the input voltage) crosses a determined threshold. This threshold is determined as a function of technical parameters for the construction of the circuit. These technical parameters are chiefly the threshold voltage of the transistor and the characteristics of the transistors that form the locking circuit.

摘要翻译： 用于低功率集成电路的电源电压监控电路，其中通过开关电容器链的电荷共享用于将电源电压耦合到动态感测节点。 动态感应节点驱动一个半锁定，在无报警状态下稳定。 在该电路中，如果在该阶段开始时电容器的端子处的电压（该电压等于输入电压的一部分）超过确定的阈值，则在第一阶段中输出的状态切换。 该阈值被确定为用于构建电路的技术参数的函数。 这些技术参数主要是晶体管的阈值电压和形成锁定电路的晶体管的特性。

公开(公告)号：US5264742A

公开(公告)日：1993-11-23

申请号：US857959

申请日：1992-03-26

申请人： Laurent Sourgen

发明人： Laurent Sourgen

IPC分类号： G01R31/317 ,  G06F12/14 ,  G07F7/10 ,  G11C29/24 ,  G11C29/52 ,  H03K19/003

CPC分类号： G07F7/1008 ,  G01R31/31701 ,  G01R31/31719 ,  G06F12/1425 ,  G06Q20/341 ,  G06Q20/357 ,  G07F7/082 ,  G11C29/24 ,  G11C29/52 ,  G01R31/31702

摘要： In order to modify the configuration of an integrated circuit, for example to restrict access by the user to certain functions or certain pieces of data of the circuit, the integrated circuit is provided with a first electronic lock capable of being locked or unlocked during a stage for the testing of the integrated circuit and capable of being irreversibly locked after the end of the testing stage, and a second electronic lock capable of being unlocked only so long as the first lock is unlocked. In this way, the entire circuit can be tested in the form in which it is presented to the user, the locking of the locks being, so to speak, simulated during the test.

摘要翻译： 为了修改集成电路的配置，例如为了限制用户对电路的某些功能或某些数据的访问，集成电路设置有能够在一个阶段被锁定或解锁的第一电子锁 用于集成电路的测试，并且能够在测试阶段结束之后不可逆地锁定，并且只要第一锁定解锁，只能解锁锁定的第二电子锁。 以这种方式，整个电路可以以呈现给用户的形式进行测试，在测试期间锁的锁可以说是模拟的。

公开(公告)号：US5889720A

公开(公告)日：1999-03-30

申请号：US852104

申请日：1997-05-06

申请人： Mathieu Lisart ,  Laurent Sourgen

发明人： Mathieu Lisart ,  Laurent Sourgen

IPC分类号： G11C16/12 ,  H03K4/00 ,  G11C13/00

CPC分类号： H03K4/00 ,  G11C16/12

摘要： To form a ramp signal for the programming of a memory cell without losing excess voltage in a control circuit, the output of a voltage pull-up circuit is connected to the programming input using a P type transistor. It is shown that this P type transistor then charges the memory array at constant current, prompting a linear increase of the voltage. This results in preventing the memory cell that is to be programmed from being subjected to excessively sudden variations of voltage. It is shown that by acting in this way, the integrated circuit can be made to work even with very low voltages.

摘要翻译： 为了形成用于编程存储器单元的斜坡信号，而不会在控制电路中损失过多的电压，使用P型晶体管将电压上拉电路的输出连接到编程输入。 这表明该P型晶体管然后以恒定电流对存储器阵列充电，促使电压线性增加。 这导致防止被编程的存储单元经受过度突然的电压变化。 显示出通过这样的方式，即使在非常低的电压下也可以使集成电路工作。

公开(公告)号：US5850452A

公开(公告)日：1998-12-15

申请号：US509363

申请日：1995-07-31

申请人： Laurent Sourgen ,  Sylvie Wuidart

发明人： Laurent Sourgen ,  Sylvie Wuidart

IPC分类号： G06F21/22 ,  G06F1/00 ,  G06F7/76 ,  G06F21/00 ,  G09C1/00 ,  H01L27/10 ,  H04L9/00

CPC分类号： G06F7/76 ,  G06F21/62 ,  G06F21/72 ,  G06F21/75

摘要： The present invention concerns a method for the numerical scrambling by permutation of data bits in a programmable circuit comprising a control unit and at least one data bus (DBUS) to transmit data between the control unit and several memory circuits. It consists of having data on the bus either in a scrambled form or in an unscrambled form according to whether it is instructions data or not. And data in some of the memories is scrambled. The present invention also concerns a method for realising a permutation circuit.

摘要翻译： 本发明涉及一种用于通过在包括控制单元和至少一个数据总线（DBUS）的可编程电路中的数据位置换进行数字加扰的方法，以在控制单元和多个存储器电路之间传送数据。 它包括根据是否是指令数据，以加扰形式或未加扰形式在总线上进行数据。 并且一些存储器中的数据被加扰。 本发明还涉及一种用于实现置换电路的方法。

公开(公告)号：US5285415A

公开(公告)日：1994-02-08

申请号：US902209

申请日：1992-06-22

申请人： Eric Depret ,  Laurent Sourgen

发明人： Eric Depret ,  Laurent Sourgen

IPC分类号： G11C17/00 ,  G06F12/16 ,  G06K19/07 ,  G07F7/08 ,  G07F7/10 ,  G11C16/02 ,  G11C16/10 ,  H03K21/00 ,  G06K5/00 ,  G06F15/30

CPC分类号： G07F7/1008 ,  G06K19/07 ,  G06Q20/341 ,  G07F7/082 ,  G07F7/0866 ,  G11C16/102 ,  G11C16/105

摘要： An integrated circuit for a passive unit counting memory card comprises p levels (10, 11, 12) of data counting memory. The levels contain corresponding numbers of cases n.sub.1 . . . n.sub.p, a write operation being achieved in a case of an upper rank level each time all the cases of the lower rank level have been enabled, the cases of the lower levels then being erased. The circuit comprises p-1 ghost levels (21, 22) identical to the p-1 upper rank levels of the p counting levels. The addressing logic of the ghost levels is such that the cases of ghost levels are addressed in write phase simultaneously with the cases of the corresponding counting levels and, after a write phase, are addressed in erase phase simultaneously with the cases of the levels of lower rank than the one that has just been enabled.

摘要翻译： 用于无源单元计数存储卡的集成电路包括数据计数存储器的p级（10,11,12）。 级别包含相应数量的病例n1。 。 。 np，每当所有低级别的所有情况都被使能时，在高级别级别的情况下实现写入操作，则较低级别的情况然后被擦除。 该电路包括与p个计数电平的p-1个上限电平相同的p-1个重影电平（21,22）。 幽灵级别的寻址逻辑是这样的：在写入阶段，与相应的计数级别的情况同时处理鬼电平的情况，并且在写入阶段之后，在擦除阶段同时处理较低级别的情况 比刚刚启用的更高。

公开(公告)号：US4851653A

公开(公告)日：1989-07-25

申请号：US117510

申请日：1987-11-06

申请人： Gilles Limisaque ,  Laurent Sourgen

发明人： Gilles Limisaque ,  Laurent Sourgen

IPC分类号： G06F12/14 ,  G06F21/00 ,  G06F21/22 ,  G06F21/24 ,  G07F7/10

CPC分类号： G07F7/1008 ,  G06F21/31 ,  G06Q20/341 ,  G07F7/10 ,  G07F7/1083

摘要： An integrated circuit for memorizing and processing information confidentially, which includes a device for controlling access to its own functions, intended to receive a confidential code, and a time delay circuit imparting a minimum predetermined delay between two attempts at introducing a confidential code even in the event of a power cut of the circuit between attempts.

摘要翻译： 一种用于存储和处理信息的集成电路，其包括用于控制访问其自己的功能的设备，用于接收机密码，以及延迟电路，在两次尝试之间施加最小的预定延迟，即使在 事件之间的电路断电。