公开(公告)号：US20020170041A1

公开(公告)日：2002-11-14

申请号：US10032155

申请日：2001-12-20

Applicant: STMicroelectronics Limited

Inventor： Richard Shann

IPC: G06F009/45

CPC classification number: G06F8/54

Abstract: A method of forming an executable program from a plurality of object code modules, each object code module having section data, a set of relocation instructions and one or more symbols, each symbol having a plurality of attributes associated therewith, wherein said relocation instructions includes a data retrieval instruction having a symbol field identifying a symbol and an attribute field identifying a symbol attribute associated with said identified symbol to be retrieved, the method includes: reading at least one relocation from said set of relocations instruction and where said relocation instruction is a data retrieval instruction, determining the symbol identified by the symbol field and retrieving one of said plurality of symbol attributes associated with said symbol in dependence on the contents of the symbol attributes field of said instruction.

Abstract translation: 一种从多个目标代码模块形成可执行程序的方法，每个目标代码模块具有分段数据，一组重定位指令和一个或多个符号，每个符号具有与之相关联的多个属性，其中所述重定位指令包括 具有标识符号的符号字段的数据检索指令和标识与要检索的所述识别符号相关联的符号属性的属性字段，所述方法包括：从所述重定位指令集中读取至少一个重定位，并且其中所述重定位指令是数据 检索指令，确定符号字段识别的符号，并根据所述指令的符号属性字段的内容，检索与所述符号相关联的所述多个符号属性中的一个。

公开(公告)号：US20020125917A1

公开(公告)日：2002-09-12

申请号：US10143417

申请日：2002-05-10

Applicant: STMicroelectronics Limited

Inventor： William Barnes

IPC: H03F003/45

CPC classification number: H03K5/249 ,  H03K3/356139 ,  H03K5/2481

Abstract: A comparator circuit with comparing means for comparing first and second voltages, has current source circuitry for providing current to said comparing means, said current source circuitry having an input for receiving a clock signal having first and second states, whereby the comparing means starts to compare the first and second voltages when the clock signal makes a transition from the first state to the second state; and means for determining when said comparing means has completed a comparison of said first and second voltages and for switching off said current source circuitry and hence said comparing means when said comparison has been completed.

Abstract translation: 具有用于比较第一和第二电压的比较装置的比较器电路具有用于向所述比较装置提供电流的电流源电路，所述电流源电路具有用于接收具有第一和第二状态的时钟信号的输入，由此比较装置开始比较 当时钟信号从第一状态转变到第二状态时的第一和第二电压; 以及用于确定何时所述比较装置已经完成了所述第一和第二电压的比较并且用于当所述比较完成时关闭所述电流源电路以及因此所述比较装置的装置。

公开(公告)号：US6163468A

公开(公告)日：2000-12-19

申请号：US302313

申请日：1999-04-29

Applicant: William Bryan Barnes

Inventor： William Bryan Barnes

IPC: G05F3/26 ,  H02M7/00

CPC classification number: G05F3/262

Abstract: A start-up circuit applies a start-up current to a current generator. The start-up circuit includes an application circuit for applying the start-up current to the current generator and an ensuring circuit ensuring that the current generator is in a predetermined stable state before the start-up current is applied thereto. The ensuring circuit prevents a flow of current in the current generator prior to application of the start-up current so that the stable state is one in which current is not conducting.

Abstract translation: 启动电路将启动电流施加到电流发生器。 启动电路包括用于将启动电流施加到电流发生器的应用电路和确保电路，确保电流发生器在施加启动电流之前处于预定的稳定状态。 确保电路在施加启动电流之前防止电流发生器中的电流流动，使得稳定状态是电流不导通的状态。

公开(公告)号：US08564333B2

公开(公告)日：2013-10-22

申请号：US12822881

申请日：2010-06-24

Applicant: Mark Trimmer

Inventor： Mark Trimmer

IPC: H03K5/19

CPC classification number: H03K5/19 ,  G06F1/14 ,  H03K5/26

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract translation: 提供了一种用于检测时钟信号上的不良时钟状况的电路和方法，该时钟信号包括在时钟信号的上升沿之后的第一多个时间延迟上对时钟信号的值进行采样。 该方法还包括在时钟信号的下降沿之后的第二多个时间延迟中对时钟信号的值进行采样。

公开(公告)号：US08391483B2

公开(公告)日：2013-03-05

申请号：US12879830

申请日：2010-09-10

Applicant: Andrew R. Dellow

Inventor： Andrew R. Dellow

IPC: H04N7/167

CPC classification number: H04N21/462 ,  H04N5/76 ,  H04N5/913 ,  H04N21/4334 ,  H04N21/434 ,  H04N21/4408 ,  H04N2005/91364

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table. When they are equal, the corresponding DES key value is read from the table and provided as an output. The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.

公开(公告)号：US08191125B2

公开(公告)日：2012-05-29

申请号：US11016537

申请日：2004-12-17

Applicant: Andrew Dellow ,  Rodrigo Cordero

Inventor： Andrew Dellow ,  Rodrigo Cordero

IPC: G06F21/00

CPC classification number: H04N21/4181 ,  G06F21/85 ,  H04N7/162 ,  H04N21/454

Abstract: An embodiment comprises a semiconductor integrated circuit for restricting the rate at which data may be accessed from an external memory by a device coupled to the circuit. The rate of data access is restricted if the data access satisfies one or more conditions. For example, one of the conditions is that the device which is requesting the data is insecure. Another condition is that the requested data is privileged. A data access monitor is provided to monitor data accesses and to is arranged to generate an access signal to indicate whether the conditions are satisfied or not. A bandwidth comparator determines whether data access exceeds a threshold and, if so, the semiconductor integrated circuit is impaired to prevent further data access.

Abstract translation: 一个实施例包括半导体集成电路，用于通过耦合到该电路的装置来限制可从外部存储器访问数据的速率。 如果数据访问满足一个或多个条件，则数据访问速率受到限制。 例如，其中一个条件是请求数据的设备是不安全的。 另一个条件是请求的数据是特权的。 提供数据访问监视器以监视数据访问，并且被布置成生成访问信号以指示条件是否满足。 带宽比较器确定数据访问是否超过阈值，如果是，则削弱半导体集成电路以防止进一步的数据访问。

公开(公告)号：US07929655B2

公开(公告)日：2011-04-19

申请号：US12481375

申请日：2009-06-09

Applicant: Matthew Peter Hutson

Inventor： Matthew Peter Hutson

IPC: H04L25/38 ,  H04L7/00

CPC classification number: H04L7/02

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract translation: 一种用于控制第一时钟域中的信号序列向多个其它时钟域的传送的系统。 该系统包括：检测电路，用于检测来自时钟域的信号的接收，并且当从时钟域接收的所有信号具有共同的状态时，设置更新信号; 以及用于接收更新信号的选通电路，并且当更新信号被设置时可操作以允许序列中的下一个信号在第一电路的输入处被接收。

公开(公告)号：US20100254405A1

公开(公告)日：2010-10-07

申请号：US12762132

申请日：2010-04-16

Applicant: Steven Haydock

Inventor： Steven Haydock

IPC: H04J3/00

CPC classification number: H04N21/235 ,  H04N21/434 ,  H04N21/435

Abstract: A data transport device for transporting a data stream, the device including: a data stream processing unit for receiving an input data stream including a plurality of data items, performing processing in dependence on the content of the items and forming an output data stream including at least some of the data items; and a data item injection unit including a memory for storing a plurality of injection data items and associated with each injection data item an injection action, and an injection processor arranged to retrieve the injection action for each of the injection data items in turn and in dependence on the retrieved injection action to inject the associated injection data item into the output data stream.

Abstract translation: 一种用于传送数据流的数据传输装置，该装置包括：数据流处理单元，用于接收包括多个数据项的输入数据流，根据项目的内容执行处理，并形成包括在 最少的一些数据项; 以及数据项目注入单元，其包括用于存储多个注射数据项并且与每个注射数据项相关联的注射动作的存储器，以及喷射处理器，其被配置为依次检索每个注射数据项的注射动作 在检索到的注入动作上将相关联的注入数据项注入到输出数据流中。

公开(公告)号：US07796755B2

公开(公告)日：2010-09-14

申请号：US11522118

申请日：2006-09-15

Applicant: Andrew R. Dellow

Inventor： Andrew R. Dellow

IPC: H04N7/167

CPC classification number: H04N21/462 ,  H04N5/76 ,  H04N5/913 ,  H04N21/4334 ,  H04N21/434 ,  H04N21/4408 ,  H04N2005/91364

Abstract: A device for locating a DES key value that corresponds to a packet identification (PID) contained at a variable possible location which comprises part only of a 32-bit packet header. A table stored in memory contains for each DES key: (i) a packet header having 32 bits with a PID of either 12, 9 or 8 bits contained at a defined location and with zero values elsewhere, and (ii) a mask value also having 32 bits with ones contained at the said defined location of the PID and zeros elsewhere. The table is divided into regions for respective packet format types. An incoming packet header at an input is combined with a first one of the mask values from the table to provide a combined value that consists of the value held in the input packet header at the defined location and zeros elsewhere. This combined value is compared with the corresponding packet header stored in the table. When they are not equal, the combining and comparison is repeated for the next row of the table. When they are equal, the corresponding DES key value is read from the table and provided as an output. The system can cope with variable PID formats within the packet header without alteration to the hardware but merely with re-programming of the table contents.

Abstract translation: 用于定位对应于包含在可变可能位置的分组标识（PID）的DES密钥值的设备，该可变位置仅包括32位分组报头的一部分。 存储在存储器中的表包含每个DES密钥：（i）具有32位的分组报头，其中包含在定义的位置处的12,9或8位的PID，并且在其他地方具有零值，以及（ii）掩码值 具有32位，其中包含在PID的所述定义的位置处，并且其他地方具有零。 该表被分成用于相应分组格式类型的区域。 在输入处的输入分组报头与表中的第一个掩码值组合，以提供组合值，该组合值由保存在定义位置的输入分组报头中的值和其他地方的零组成。 将该组合值与存储在表中的相应分组报头进行比较。 当它们不相等时，对于表的下一行重复组合和比较。 当它们相等时，从表中读取相应的DES密钥值作为输出。 该系统可以处理数据包头中的可变PID格式，而不会改变硬件，但只能对表内容进行重新编程。

公开(公告)号：US07720112B2

公开(公告)日：2010-05-18

申请号：US10779466

申请日：2004-02-16

Applicant: Matt Morris

Inventor： Matt Morris

IPC: H04J3/04

CPC classification number: H04L49/25 ,  H04L49/103

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract translation: 讨论数据流的路由，并且特别地将一个或多个输入流路由到一个或多个输出目的地端口。 讨论合并输入流的能力，使得几个低比特率输入分组流可以被合并到更高比特率的输出流中。 分配数据结构为每个输入流标识其要路由的每个目的地，并且分组分配数据结构保存关于分组的信息和关于分组的目的地的信息，以允许控制分组的存储器 相应地。