DC ARC DETECTION AND PHOTOVOLTAIC PLANT PROFILING SYSTEM

    公开(公告)号:US20200076364A1

    公开(公告)日:2020-03-05

    申请号:US16114571

    申请日:2018-08-28

    Abstract: An arc detection method includes classifying whether an arc fault is present in the power system by, for each of a plurality of bins of a current frame of a signal, marking the bin as a candidate bin if a magnitude spectrum of the bin meets first criteria; determining a number of candidate bins in the current frame; marking the number of candidate bins as candidate cluster bins if the number of candidate bins exceeds a minimum cluster size; for each of the candidate cluster bins, determining whether the candidate cluster bin is also a candidate cluster bin of a previous frame of the first signal and if so, identifying the current frame as a candidate frame and incrementing a candidate frame count; and if the candidate frame count exceeds a candidate frame count threshold, determining that an arc fault is present in the power system.

    POWER ISOLATOR EXHIBITING LOW ELECTROMAGNETIC INTERFERENCE

    公开(公告)号:US20200036284A1

    公开(公告)日:2020-01-30

    申请号:US16046732

    申请日:2018-07-26

    Abstract: Power isolators for providing electrical isolation between an input port and an output port that exhibit low electromagnetic interference (EMI) are described. The low EMI may be achieved by, for example, canceling out a common mode current across a transformer in the power isolator that may be converted into EMI. The power isolator may include at least one oscillator circuit that is configured to apply a first signal to a first transformer and a second, different signal to a second transformer. The first and second signals may be configured such that the common mode current generated in each of the first and second transformers has an opposite direction. Thus, the common mode currents in the first and second transformers may at least partially cancel out. As a result, the EMI exhibited by the power isolator may be reduced.

    Auxiliary input for analog-to-digital converter input charge

    公开(公告)号:US10541702B1

    公开(公告)日:2020-01-21

    申请号:US16142964

    申请日:2018-09-26

    Abstract: Input stages for an analog to digital converter wherein charge for charging parasitic capacitances in the input stage, and particularly in the input switch is sourced from a node which means that it does not have to pass through the input RC filter. This has the effect that the input RC filter can be of lower bandwidth, and/or have a larger resistor value, with the consequent result that there is lower power dissipation in the ADC drive circuitry. In one example this effect is realized by providing a separate input into which charge to charge the parasitic capacitances can be fed from external circuitry. In another example an operational amplifier having high (ideally infinite) input impedance can be used to feed charge to the input switch from the input to the RC filter, or from the node between the resistor and capacitor of the filter, again without unsettling the filter.

    REDUCING MOTION-RELATED ARTIFACTS IN OPTICAL MEASUREMENTS FOR VITAL SIGNS MONITORING

    公开(公告)号:US20200015753A1

    公开(公告)日:2020-01-16

    申请号:US16033310

    申请日:2018-07-12

    Abstract: Vital sign monitors are plagued by noisy photoplethysmography (PPG) data, making it difficult for the monitors to output consistently accurate readings. Noise in PPG signals is often caused by motion. The present disclosure provides improved techniques for reducing motion-related artifacts in optical/PPG measurements for vital signs monitoring. In general, techniques described herein are based on using measurements of reference sensors that include sensors other than optical sensors used for the optical measurements, e.g., biopotential sensors, bioimpedance sensors, and/or capacitive sensors. In particular, techniques described herein aim to filter PPG signals using substantially only the noise components of signals generated by reference sensors, by attenuating or altogether eliminating components of the signals generated by reference sensors which are indicative of the parameter the reference sensors are designed to measure. Implementing the techniques described herein may lead to more accurate vital sign evaluation using optical/PPG measurements.

    TECHNIQUES FOR SWITCH CAPACITOR REGULATOR POWER SAVINGS

    公开(公告)号:US20190341844A1

    公开(公告)日:2019-11-07

    申请号:US15968981

    申请日:2018-05-02

    Abstract: Techniques for improving efficiency of a switched-capacitor voltage regulator are provided. In an example, a switched-capacitor voltage regulator can include a switched-capacitor network having multiple gain configurations, a clock configured to switch capacitors of the switched-capacitor network between a charge state and a discharge state to provide a scaled output voltage, and a controller configured to select a capacitor configuration associated with a gain of the multiple gain configurations to provide the scaled output voltage within a desired output voltage range while continuously switching the capacitor configuration, and to interrupt switching of the capacitor configuration to permit an output voltage of the switched-capacitor voltage regulator to fall below the scaled output voltage but to remain above a lower limit of the desired output voltage range to save power by reducing losses due to the switching.

    LOW QUIESCENT CURRENT POWER ON RESET CIRCUIT
    58.
    发明申请

    公开(公告)号:US20190319616A1

    公开(公告)日:2019-10-17

    申请号:US15954204

    申请日:2018-04-16

    Abstract: A device for providing a reset signal to one or more sequential logic circuits in an electronic system responsive to a supply voltage condition includes a first voltage detector circuit to generate a first pulse after the supply voltage rises to a first threshold voltage level. The device further includes a second voltage detector circuit to generate a second pulse after the supply voltage falls below a second threshold voltage level. The device additionally includes a latch circuit to store a first value based on the first pulse after the supply voltage rises to the first threshold voltage level, disable the first voltage detector circuit after storing the first value, reset to store a second value based on the second pulse after the supply voltage falls below the second threshold voltage level, and to disable the second voltage detector circuit after the resetting.

    LOW POWER HALF-VDD GENERATION CIRCUIT WITH HIGH DRIVING CAPABILITY

    公开(公告)号:US20190317541A1

    公开(公告)日:2019-10-17

    申请号:US15951894

    申请日:2018-04-12

    Abstract: A common mode reference circuit comprises a divider stage and an output stage. The divider stage includes a first n-channel field effect transistor and p-channel filed effect transistor (NFET/PFET) pair connected in series to a high supply voltage circuit node; and a second NFET/PFET pair connected in series to a low supply voltage circuit node. The output stage includes a first FET connected as a current mirror to a transistor of the first NFET/PFET pair; a second FET connected as a current mirror to a transistor of the second NFET/PFET pair; and a common mode reference output at a series connection from the first FET to the second FET.

    SYSTEM AND METHOD TO REDUCE DATA HANDLING ON LITHIUM ION BATTERY MONITORS

    公开(公告)号:US20190302191A1

    公开(公告)日:2019-10-03

    申请号:US16447539

    申请日:2019-06-20

    Abstract: An example method to reduce data handling on lithium ion battery monitors is provided and includes receiving a request from a micro-controller for data associated with one or more cells, receiving signals corresponding to monitored properties from the cells, calculating derivative properties from the monitored properties, dividing a default data into a plurality of portions, and sending the derivative properties and one of the portions to the micro-controller according to at least a first compute logic option or a second compute logic option. The default data can include cell voltages, auxiliary inputs, stack voltage, reference output voltage, analog voltage output, analog voltage input, temperature, and reference buffer voltage. The default data is provided sequentially to the micro-controller in as many consecutive read backs as the number of portions, where each portion corresponds to the default data measured at a distinct time instant.

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