Abstract:
In a method of inputting/outputting data in a semiconductor memory device, first data and second data are buffered and outputted to a first output node and a second output node, respectively, in a normal mode. In a test mode, the first data is buffered through a first transmission line and a second transmission line and outputted to the first output node and the second output node in response to at least one control signal. Also, in the test mode, the second data is buffered through the first transmission line and the second transmission line and outputted to the first output node and the second output node in response to the at least one control signal. Accordingly, test time may be reduced, and variations of operation characteristics caused by merging the data pins may also be reduced.
Abstract:
A method of manufacturing a gelatin shape collagen food, which contains a tendon structure therein, is provided. The method is comprised of: 1) boil tendons from a cow in water for 90 minutes, 2) quench the tendon with cold water at 15° C., 3) rip off meats from the tendons, 4) slice the tendons in a shape with a 5 mm thickness, 1 cm width and 10 cm length. At the same time 5) boil cow's pettitoe in water for one hour, 6) rip off skin of the cow pettitoe and remove fats by hand, 7) boil the cow's pettitoe again in water for 30 minutes to remove residual fat, 8) mix the sliced tendons and ripped off pettitoe in water in 1:1:4 volume ratios, add caramel drop, gelatin powders and apple cider, 9) boil down the mixtures prepared in the eighth step slowly for 1.5 hours, 10) put the mixture in a mold and quench as soon as possible, 11) dry out the gelatin structure by blowing air at room temperature for four hours, and 12) cut the gelatin structure into desired size.
Abstract:
Provided is an apparatus and method for controlling a voltage gain in an ultra wideband receiving apparatus. The apparatus includes a register for storing an Automatic Gain Control (AGC) value detected in a section where an AGC operation control signal is “ON”; and a voltage gain controller for generating a voltage gain control value by reading the AGC stored in the register during a section where a reception enable signal is “ON”, and transferring the generated voltage gain control value to a voltage gain amplifier.
Abstract:
Provided is a method for transforming data using a look-up table. The method includes the steps of: (a) mapping preprocessed input binary data to a constellation diagram divided into four quadrants to output a first complex number; (b) performing addition/subtraction operations between real numbers and between imaginary numbers with respect to the first complex number and a second complex number; and (c) reading a fourth complex from a look-up table in response to the first complex number, the second complex number and a third complex number, the look-up table outputting the fourth complex by performing a subtraction operation on multiplication results between real numbers and between imaginary numbers and an addition operation on multiplication results between the real numbers and the imaginary numbers with respect to the result value of the step (b) and the third complex number. Accordingly, it is possible to reduce the hardware size at the time of IFFT/FFT design and to provide a high-speed, low-power operation.
Abstract:
Disclosed are a metal case for a portable terminal and a method for manufacturing the same. The metal case for the electronic device is manufactured by a method including manufacturing an initial metal case using electro-forming method; trimming the initial metal case or removing foreign material from the initial metal case, to form a shape of the metal case; and insert-injecting plastic material for an inner and/or outer surface of the metal case.
Abstract:
Provided is a method for adjusting Fast Fourier Transform (FFT) window positioning in a Multi Band Orthogonal Frequency Division Multiplexing Ultra-Wideband (MB-OFDM UWB) system. The method includes the steps of acquiring an initial FFT window position and a frequency hopping position, demodulating a received signal by using the initial FFT window position and the frequency hopping position acquired in the acquiring step, transmitting received data information to a Media Access Control (MAC) layer with a reception frame (RX frame) structure and judging at the MAC layer whether or not a packet error is occurred based on Frame Check Sequences (FCSs), and if no packet error is occurred, returning to the demodulating step, and if the packet error is occurred, changing a register map by using a predetermined interface line in a MAC-physical layer (MAC-PHY) interface to thereby adjust the FFT window position and the frequency hopping position, and then returning to the demodulating step.
Abstract:
There is provided a reliable method for sensing a laundry amount and a method for controlling a washing machine, in which a method for sensing a laundry amount is performed appropriately according to the laundry amount. According to the method of the present invention, the reliability in the sensed laundry amount is improved.
Abstract:
A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.
Abstract:
Disclosed is a layout method for increasing pitches between bit lines and between sense amplifiers so as to easily accomplish fabrication of a semiconductor memory device and a semiconductor memory array capable of reducing the number of sense amplifiers. The semiconductor memory array includes a plurality of bit lines, and a plurality of sense amplifiers, each sense amplifier being connected to each pair of the bit lines, wherein the sense amplifiers placed in each column make up each group, with odd pairs of the bit lines being connected to even or odd sense amplifier groups, and even pairs of the bit lines being connected to even or odd sense amplifier groups.
Abstract:
A flash writing circuit for testing of dynamic random access memory (DRAM) devices comprises a generally conventional DRAM device and includes additional elements for writing identical data in each memory cell via bit lines connected to the memory cells but without the use of the conventional I/O lines normally used to write data into the memory cells.