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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5610869A

    公开(公告)日：1997-03-11

    申请号：US511815

    申请日：1995-08-07

    申请人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    发明人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    IPC分类号： G11C5/14 ,  H02M3/07 ,  G11C13/00

    CPC分类号： H02M3/07 ,  G11C5/145

    摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

    摘要翻译： 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5446697A

    公开(公告)日：1995-08-29

    申请号：US068547

    申请日：1993-05-28

    申请人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    发明人： Seung-Moon Yoo ,  Ejaz ul Haq ,  Yun-Ho Choi ,  Soo-In Cho ,  Dae-Je Chin ,  Nam-Soo Kang ,  Seung-Hun Lee

    IPC分类号： G11C5/14 ,  H02M3/07 ,  G11C13/00

    CPC分类号： H02M3/07 ,  G11C5/145

    摘要： A semiconductor memory device stably operates over a wide range of the power supply voltage by including a power supply voltage level detector for generating detecting signals according to predetermined levels of the power supply voltage and an oscillator for generating a frequency-controlled oscillation pulse whose frequency is changeable according to the detecting signals. Thus, a boosting ratio of a boosting circuit, the refresh period of a refresh circuit and the substrate voltage of a substrate voltage generator can be adaptively changeable according to the variation of the power supply voltage.

    摘要翻译： 半导体存储器件通过包括用于根据电源电压的预定电平产生检测信号的电源电压电平检测器和用于产生频率为...的频率控制的振荡脉冲的振荡器，稳定地在宽范围的电源电压下工作 根据检测信号可变。 因此，升压电路的升压比，刷新电路的刷新周期和基板电压发生器的基板电压可以根据电源电压的变化自适应地变化。

    Semiconductor memory device having a plurality of row address strobe signals
    4.
    发明授权
    Semiconductor memory device having a plurality of row address strobe signals 失效
    具有多个行地址选通信号的半导体存储器件

    公开(公告)号：US5343438A

    公开(公告)日：1994-08-30

    申请号：US9475

    申请日：1993-02-01

    申请人： Yun-Ho Choi ,  Dae-Je Chin ,  Ejaz U. Haq ,  Soo-In Cho

    发明人： Yun-Ho Choi ,  Dae-Je Chin ,  Ejaz U. Haq ,  Soo-In Cho

    IPC分类号： G11C11/401 ,  G06F12/02 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C11/4076

    摘要： The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory for accomplishing high speed data access by supplying a plurality of row address strobe signals to a chip. A plurality of row address strobe signals are supplied to a plurality of pins, and each row address strobe signal is sequentially supplied with an active signal during a data access operation. Therefore, data in a plurality of memory cell arrays is accessed during one access cycle time. Thus, since a large number of random data are provided, the data access time decreases and the performance of a system can be greatly improved.

    摘要翻译： 本发明涉及一种半导体存储器件，更具体地说，涉及通过向芯片提供多个行地址选通信号来实现高速数据存取的动态随机存取存储器。 多个行地址选通信号被提供给多个引脚，并且每个行地址选通信号在数据访问操作期间被依次提供有效信号。 因此，在一个访问周期时间内访问多个存储单元阵列中的数据。 因此，由于提供大量随机数据，所以数据访问时间减少，并且可以大大提高系统的性能。

    Multi-bank dynamic random access memory devices having all bank precharge capability
    5.
    发明授权
    Multi-bank dynamic random access memory devices having all bank precharge capability 有权
    具有全部预充电能力的多组动态随机存取存储器件

    公开(公告)号：US06343036B1

    公开(公告)日：2002-01-29

    申请号：US09157271

    申请日：1998-09-18

    申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC分类号： G11C700

    CPC分类号： G11C7/1018 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C2207/2281

    摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平是第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的去激活信号，使得响应于激活信号的所选存储器组在活动周期中工作，而未被选择的存储器组响应于 灭活信号在预充电循环中工作。

    Semiconductor memory having a plurality of I/O buses
    6.
    发明授权
    Semiconductor memory having a plurality of I/O buses 失效
    具有多个I / O总线的半导体存储器

    公开(公告)号：US5590086A

    公开(公告)日：1996-12-31

    申请号：US580481

    申请日：1995-12-29

    申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Circuit in a semiconductor memory for programming operation modes of the memory
    8.
    发明授权
    Circuit in a semiconductor memory for programming operation modes of the memory 失效
    用于存储器的编程操作模式的半导体存储器中的电路

    公开(公告)号：US5838990A

    公开(公告)日：1998-11-17

    申请号：US905562

    申请日：1997-08-04

    申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F9/00 ,  G06F13/16

    CPC分类号： G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Synchronous dram having a plurality of latency modes
    9.
    发明授权
    Synchronous dram having a plurality of latency modes 失效
    具有多个等待时间模式的同步电话

    公开(公告)号：US5835956A

    公开(公告)日：1998-11-10

    申请号：US822148

    申请日：1997-03-17

    申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G06F13/16

    CPC分类号： G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

    Semiconductor memory
    10.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5703828A

    公开(公告)日：1997-12-30

    申请号：US580622

    申请日：1995-12-29

    申请人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    发明人： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

    CPC分类号： G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    摘要： A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    摘要翻译： 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。