公开(公告)号：US20070097902A1

公开(公告)日：2007-05-03

申请号：US11294146

申请日：2005-12-05

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Montuno ,  Kent Felske

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Montuno ,  Kent Felske

IPC: H04B7/212

CPC classification number: H04J3/0658

Abstract: Where a common network clock is available at both a TDM receiver and a TDM transmitter which communicate via a packet network, differential clock recovery can be accomplished by matching the number of service clock pulses in a network reference clock period at the transmitter and receiver. In one embodiment the transmitter need only send a counter value from a counter that is clocked and reset, respectively, by the service clock and network reference clock, thereby allowing use of different types of oscillators, both analog and digital, to be implemented at the transmitter and receiver. The technique is also general enough to be applied in a wide variety of packet networks including but not limited to IP, MPLS and Ethernet. In an alternative embodiment, a faster derived network clock fdnc drives both the transmitter and receiver counters, which in turn are reset, respectively by the slower transmitter service clock fsc and slower receiver service clock frc.

Abstract translation: 在通过分组网络进行通信的TDM接收机和TDM发射机都可以使用公共网络时钟的情况下，差分时钟恢复可以通过在发射机和接收机的网络参考时钟周期内匹配服务时钟脉冲的数量来实现。 在一个实施例中，发射机仅需要通过服务时钟和网络参考时钟分别从计时器发送计数器值并将其复位，从而允许使用不同类型的模拟和数字振荡器来实现 发射机和接收机。 该技术也足以应用于各种分组网络，包括但不限于IP，MPLS和以太网。 在替代实施例中，更快的导出网络时钟fndnc驱动发射机和接收机计数器，发射机和接收机计数器又分别由较慢的发射机业务时钟f SC和 较慢的接收机服务时钟f 。

公开(公告)号：US07191355B1

公开(公告)日：2007-03-13

申请号：US10888421

申请日：2004-07-09

Applicant: Michel Ouellette ,  Jeganathan Markandu ,  James Aweya ,  Delfin Montuno

Inventor： Michel Ouellette ,  Jeganathan Markandu ,  James Aweya ,  Delfin Montuno

IPC: G06F1/12 ,  H04L12/28

CPC classification number: G06F1/12 ,  H04J3/0632 ,  H04L2012/6489

Abstract: A clock synchronization backup mechanism is disclosed for maintaining clock synchronization during periods of degraded synchronization. The clock synchronization backup mechanism includes a jitter buffer having a fill value at a given sample time which is compared with a threshold. When the jitter buffer fill value exceeds the threshold, a non-normal condition is registered and the local clock frequency is set to a combination of a long-term frequency setting plus a threshold sensitive frequency adjustment. The clock synchronization backup mechanism is particularly useful for overcoming residual errors accumulated due to temperature change, oscillator degradation, and a variety of other system perturbations problematical for clock synchronization mechanisms known in the art.

Abstract translation: 公开了一种时钟同步备份机制，用于在降级同步期间维持时钟同步。 时钟同步备份机制包括抖动缓冲器，该抖动缓冲器在给定采样时间具有与阈值进行比较的填充值。 当抖动缓冲区填充值超过阈值时，注册非正常条件，并将本地时钟频率设置为长期频率设置加阈值敏感频率调整的组合。 时钟同步备份机制对于克服由于温度变化，振荡器衰减以及本领域已知的时钟同步机制的各种其他系统扰动而累积的残余误差特别有用。

公开(公告)号：US20060242445A1

公开(公告)日：2006-10-26

申请号：US11394705

申请日：2006-03-31

Applicant: James Aweya ,  Delfin Montuno ,  Michel Ouellette ,  Kent Felske

Inventor： James Aweya ,  Delfin Montuno ,  Michel Ouellette ,  Kent Felske

IPC: H03D3/24 ,  G06F1/12

CPC classification number: H03L7/08 ,  H03L2207/50

Abstract: A method and apparatus for designing a PLL enables initial component characteristics and design specifications of the PLL to be specified. Time constants for a loop filter that would be required to create a PLL having the desired design specifications and component characteristics are then computed. The performance or behavior characteristics of the PLL may then be computed for the PLL given the time constants and the initial set of components, to determine whether the performance of the PLL would be considered satisfactory. For example, PLL design software may determine whether a PLL would be sufficiently stable if it was to be created using the particular selected components given the required design specifications. Where the PLL does not meet particular behavior characteristics, the PLL design software may provide guidance as to what component characteristics would improve performance of the PLL. Designed PLLs may be used for timestamp based clock synchronization.

公开(公告)号：US07047312B1

公开(公告)日：2006-05-16

申请号：US09739309

申请日：2000-12-18

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC: G06F15/16

CPC classification number: H04L47/2441 ,  H04L1/1832 ,  H04L47/10 ,  H04L47/193 ,  H04L47/25 ,  H04L47/27 ,  H04L47/29 ,  H04L47/30 ,  H04L47/35 ,  H04L69/16 ,  H04L69/163

Abstract: The TCP receiver's advertised window (i.e., the receive buffer of a TCP connection) limits the maximum window and consequently the throughput that can be achieved by the sender. Thus, the idea behind TCP rate control is to match the offered network load to the available resources by modifying at an intermediate network device, the receiver's advertised window in TCP acknowledgments returning to the sources. In this disclosure, we propose a new TCP rate control scheme for a shared buffer where the buffer is logically organized into multiple queues. In the scheme, dynamic buffer thresholds are used to ensure efficient and fair usage of buffer memory among the queues. Conventional schemes allocate buffer space to each queue through the use of static buffer thresholds. This can result in unnecessary packet drops which leads to poor network performance since congested or heavily loaded queues cannot gain access to buffers not utilized by lightly loaded queues.

Abstract translation: TCP接收方的通告窗口（即TCP连接的接收缓冲区）限制了最大窗口，从而限制了发送方可以实现的吞吐量。 因此，TCP速率控制背后的想法是通过在中间网络设备修改接收者在TCP回复到源的确认窗口中，将提供的网络负载与可用资源进行匹配。 在本公开中，我们提出了一种用于共享缓冲器的新的TCP速率控制方案，其中缓冲器被逻辑地组织成多个队列。 在该方案中，使用动态缓冲器阈值来确保队列之间缓冲存储器的有效和合理使用。 传统方案通过使用静态缓冲区阈值为每个队列分配缓冲区空间。 这可能会导致不必要的数据包丢失，从而导致网络性能不佳，因为拥塞或负载较重的队列无法访问未被轻载队列使用的缓冲区。

公开(公告)号：US20060056560A1

公开(公告)日：2006-03-16

申请号：US11172100

申请日：2005-06-30

Applicant: James Aweya ,  Delfin Montuno ,  Michel Ouellette ,  Kent Felske

Inventor： James Aweya ,  Delfin Montuno ,  Michel Ouellette ,  Kent Felske

IPC: H04L7/00

CPC classification number: H03L7/0992 ,  H04J3/0664

Abstract: A first level of control over operation of slave Digitally Controlled Frequency Selectors (DCFSs), such as DCOs or DDSs, may occur by periodic transmission of control words from the master clock to the slave clocks. To allow enhanced control over the output of the slave clocks, the frequency of the local oscillator used to generate the synthesized output of the master clock may also be conveyed to the slave clocks to allow a second level of control to take place. The second level of control allows the local oscillators at the slave clocks to lock onto the frequency of the master local oscillator to thereby allow the slave local oscillators to operate the slave DCFSs using the same local oscillator frequency. The first level of control synchronizes operation of the DCFSs while the second level control prevents instabilities in the local oscillators from causing long term drift between the slave and master clock outputs. Timestamps may be used to synchronize the master and slave local oscillators.

公开(公告)号：US06901593B2

公开(公告)日：2005-05-31

申请号：US09850057

申请日：2001-05-08

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC: G06F9/00 ,  H04L12/56

CPC classification number: H04L49/90 ,  H04L47/10 ,  H04L47/12 ,  H04L47/29 ,  H04L47/32 ,  H04L49/9078

Abstract: A technique for an improved active queue management scheme which dynamically changes its threshold settings as the number of connections (and system load) changes is disclosed. Using this technique, network devices can effectively control packet losses and TCP timeouts while maintaining high link utilization. The technique also allows a network to support a larger number of connections during congestion periods.

Abstract translation: 一种用于改进的主动队列管理方案的技术，其公开了连接数（和系统负载）变化的动态地改变其阈值设置。 使用这种技术，网络设备可以有效地控制分组丢失和TCP超时，同时保持较高的链路利用率。 该技术还允许网络在拥塞期间支持更大数量的连接。

公开(公告)号：US06549517B1

公开(公告)日：2003-04-15

申请号：US09209273

申请日：1998-12-11

Applicant: James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

Inventor： James Aweya ,  Michel Ouellette ,  Delfin Y. Montuno

IPC: H04L1206

CPC classification number: H04L49/3081 ,  H04L2012/5635 ,  H04Q11/0478

Abstract: Flow control in a network is implemented based on aggregate traffic measurements. For example, in an ATM network only the aggregate background (CBR/VBR) traffic rate and the aggregate ABR traffic rate are used, in contrast with other schemes that require per-connection rate measurements or variables. An explicit rate is calculated recursively at discrete time instances using a scaled error value which is generated in response to an aggregate ABR input rate and a desired traffic rate. Explicit rate computations can be performed entirely by software, and the interval between computations is large enough to keep the processing overhead required of the switch very low. In addition, methods consistent with the present invention achieve max-min fairness and MCR plus equal share in a natural way without any additional computation or information about bottleneck rates.

Abstract translation: 基于总流量测量实现网络中的流量控制。 例如，在ATM网络中，与使用每连接速率测量或变量的其他方案相比，仅使用聚合背景（CBR / VBR）流量速率和聚合ABR流量速率。 使用响应于总ABR输入速率和期望业务速率而产生的缩放误差值，以离散时间实例递归地计算显式速率。 显式速率计算可以完全由软件执行，并且计算之间的间隔足够大，以保持开关所需的处理开销非常低。 此外，与本发明一致的方法可以以自然的方式实现max-min公平性和MCR加上相等的份额，而无需任何额外的计算或关于瓶颈率的信息。

公开(公告)号：US09178464B2

公开(公告)日：2015-11-03

申请号：US13699810

申请日：2012-09-04

Applicant: James Aweya ,  Nayef AlSindi

Inventor： James Aweya ,  Nayef AlSindi

IPC: H02P29/00 ,  H02P5/46 ,  H02P23/00 ,  H02P5/74

CPC classification number: H02P29/0005 ,  H02P5/46 ,  H02P5/74 ,  H02P23/22

Abstract: This invention relates to methods and devices for motor speed control. The invention has particular application in the control of motors over packet networks. In embodiments of the invention, phase-locked loop principles are used to remotely control the speed of an electric motor over a packet network. The setpoint for the motor is supplied by arriving timestamps from a speed-mapped variable frequency source. The shaft speed of the motor is measured with a tachometer with its output proportional to the motor speed. Any deviation of the actual speed from the setpoint is amplified by the power amplifier whose output drives the motor. Speed control over packet networks allow smoother operation of a process, acceleration control, different operating speeds for each process recipe, compensation for changing process variables, slow operation for setup purposes, adjustments to the rate of production, accurate positioning, and control torque or tension of a system.

Abstract translation: 本发明涉及电机速度控制的方法和装置。 本发明特别适用于通过分组网络控制电动机。 在本发明的实施例中，使用锁相环原理来远程控制分组网络上的电动机的速度。 电机的设定值由速度映射的可变频率源的到达时间戳提供。 电机轴转速用转速计测量，其转速与电机转速成比例。 实际速度与设定值的任何偏差由输出驱动电机的功率放大器放大。 通过分组网络的速度控制可以使流程更加顺畅，加速控制，每个过程配方的不同运行速度，改变过程变量的补偿，设定目的的缓慢操作，生产率的调整，精确的定位和控制扭矩或张力 的系统。

公开(公告)号：US08913632B2

公开(公告)日：2014-12-16

申请号：US13204079

申请日：2011-08-05

Applicant: James Aweya ,  Saleh Al Araji

Inventor： James Aweya ,  Saleh Al Araji

IPC: H04J3/06

CPC classification number: H04J3/0664 ,  H03L7/0807 ,  H03L7/099 ,  H03L7/0991 ,  H03L7/0994 ,  H03L2207/50 ,  H04J3/0667

Abstract: Systems and methods of synchronizing the frequency of a slave clock to that of a master clock using time-stamps in transmissions from a master device having the master clock, determining an error signal, and adjusting the frequency of the slave clock based on said error signal.

Abstract translation: 使用来自具有主时钟的主设备的传输中的时间戳来同步从时钟的频率与主时钟的频率的系统和方法，基于所述误差信号确定误差信号和调整从时钟的频率 。

公开(公告)号：US08880105B2

公开(公告)日：2014-11-04

申请号：US13339777

申请日：2011-12-29

Applicant: James Aweya ,  Nayef Alsindi ,  Kin Poon

Inventor： James Aweya ,  Nayef Alsindi ,  Kin Poon

IPC: H04W24/00

CPC classification number: G01S5/0252

Abstract: This invention relates to methods and devices for entropy-based location fingerprinting, in particular for use over wireless local-area networks (WLANs). The invention has particular application in localization for indoor environments. In embodiments of the invention, an entropy-based fingerprint is determined at a number of predetermined locations within the desired area of localization during an off-line phase and subsequently used in an on-line mode to determine the location of a receiver. In particular embodiments, the fingerprint is a vector of entropy estimates of the channel transfer function (CTF) between a mobile terminal and all access points within coverage. The invention seeks to provide a fingerprinting localization solution that has a simplicity of structure, leading to advantages in storage and pattern recognition requirements, and robustness by proving a unique measure of information that is related to the channel experienced at the location of the mobile terminal.

Abstract translation: 本发明涉及用于基于熵的位置指纹的方法和装置，特别是用于无线局域网（WLAN）上。 本发明在室内环境的定位中具有特别的应用。 在本发明的实施例中，在离线阶段期间，在所需的定位区域内的多个预定位置处确定基于熵的指纹，并随后以在线模式使用以确定接收机的位置。 在特定实施例中，指纹是移动终端与覆盖范围内的所有接入点之间的信道传递函数（CTF）的熵估计的向量。 本发明寻求提供一种指纹定位解决方案，其具有简单的结构，通过证明与在移动终端的位置处经历的信道相关的信息的独特测量，可以获得存储和模式识别要求的优势以及鲁棒性。