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    Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor
    52.
    发明申请
    Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor 失效
    用于间接访问内存映射资源的支持接口以减少带外支持处理器的系统连接的方法

    公开(公告)号：US20060176897A1

    公开(公告)日：2006-08-10

    申请号：US11055404

    申请日：2005-02-10

    申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

    发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

    IPC分类号： H04L12/66

    CPC分类号： G06F15/7842

    摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

    摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 Fabric命令转换为FSI协议，并转发到附加的支持芯片以访问内存映射资源，并将来自支持芯片的响应转换回Fabric响应数据包。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。

    Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
    53.
    发明申请
    Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes 失效
    修改的无效缓存状态，以减少用于推测发出的全缓存行写入的缓存到高速缓存数据传输操作

    公开(公告)号：US20050071573A1

    公开(公告)日：2005-03-31

    申请号：US10675744

    申请日：2003-09-30

    申请人： John Dodson ,  James Fields ,  Guy Guthrie ,  Kenneth Wright

    发明人： John Dodson ,  James Fields ,  Guy Guthrie ,  Kenneth Wright

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0835 ,  G06F12/0831 ,  G06F2212/507

    摘要： A cache coherency protocol that includes a modified-invalid (Mi) state, which enables execution of a DMA Claim or DClaim operation to assign sole ownership of a cache line to a device that is going to overwrite the entire cache line without cache-to-cache data transfer. The protocol enables completion of speculatively-issued full cache line writes without requiring cache-to-cache transfer of data on the data bus during a preceding DMA Claim or DClaim operation. The modified-invalid (Mi) state assigns sole ownership of the cache line to an I/O device that has speculatively-issued a DMA Write or a processor that has speculatively-issued a DCBZ operation to overwrite the entire cache line, and the Mi state prevents data being sent to the cache line from another cache since the data will most probably be overwritten.

    摘要翻译： 包括经修改的无效（Mi）状态的高速缓存一致性协议，其使得能够执行DMA声明或DClaim操作以将高速缓存行的唯一所有权分配给要覆盖整个高速缓存行的设备，而不进行高速缓存 - 缓存数据传输。 该协议允许完成推测发出的完整高速缓存行写入，而不需要在先前的DMA声明或DClaim操作期间在数据总线上缓存到高速缓存传输数据。 修改无效（Mi）状态将高速缓存行的唯一所有权分配给推测性地发出DMA写入的I / O设备或者推测发出DCBZ操作以覆盖整个高速缓存行的处理器，并且将Mi 状态可防止将数据从另一个缓存发送到高速缓存行，因为数据最有可能被覆盖。

    DOCUMENT SECURITY METHOD
    54.
    发明申请
    DOCUMENT SECURITY METHOD 审中-公开
    文件安全方法

    公开(公告)号：US20100142756A1

    公开(公告)日：2010-06-10

    申请号：US12626967

    申请日：2009-11-30

    申请人： Andrew James Fields ,  Shaun Peter O'Keefe

    发明人： Andrew James Fields ,  Shaun Peter O'Keefe

    IPC分类号： G06K9/00

    CPC分类号： G07D7/0053 ,  G06K2009/226 ,  G07D7/206

    摘要： Disclosed is a method (600) of protecting a document (715) containing document information content, the method comprising the steps of defining a regular grid (716) over the document (715), separating the grid intersection points into a repeating pattern of points (701-704), wherein each member of the repeating pattern comprises two subsets of points (705, 709) having a predefined spatial relationship, said subsets of points being associated with corresponding regions of the document (715), and modulating (506), with respect to each member of the repeating pattern (701-704), protection mark attributes of protection marks associated with one of said subsets of points (709), to thereby encode information about the document information content of the regions of the document associated with both said subsets of points (705, 709).

    摘要翻译： 公开了一种保护包含文件信息内容的文档（715）的方法（600），该方法包括以下步骤：在文档（715）上定义规则网格（716），将网格交点分隔成重复的点数 （701-704），其中所述重复图案的每个成员包括具有预定空间关系的两个点集合（705,709），所述点集合与文档（715）的相应区域相关联，并且调制（506） 相对于所述重复图案（701-704）的每个成员，与所述点的所述子集（709）相关联的保护标记的保护标记属性，从而编码关于所述文档相关区域的文档信息内容的信息 所有这两个点的分数（705,709）。

    Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response
    55.
    发明申请
    Data processing system, cache system and method for precisely forming an invalid coherency state based upon a combined response 失效
    数据处理系统，缓存系统和基于组合响应精确形成无效一致性状态的方法

    公开(公告)号：US20070226426A1

    公开(公告)日：2007-09-27

    申请号：US11388016

    申请日：2006-03-23

    申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

    发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831

    摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain includes a system memory controller for a system memory and a first processing unit having a first cache memory. The second coherency domain includes a second processing unit having a second cache memory. In the first cache memory, a coherency state field associated with a storage location and an address tag is set to a first coherency state. In response to snooping an exclusive access request specifying a target address matching the address tag, the first cache memory provides a first partial response to the exclusive access request based at least in part upon the first coherency state. In response to snooping the exclusive access request, the memory controller determines whether it is responsible for the target address and provides a second partial response to the exclusive access request based at least in part upon an outcome of the determination. At least the first and second partial responses are accumulated to obtain a combined response for the exclusive access request. The combined response includes an indication of whether or not a highest point of coherency and a memory controller of a home system memory for the target address reside within a same coherency domain. The first cache memory updates the coherency state field from the first coherency state to a second coherency state in response to the indication in the combined response.

    摘要翻译： 缓存相干数据处理系统至少包括第一和第二相干域。 第一相干域包括用于系统存储器的系统存储器控制器和具有第一高速缓冲存储器的第一处理单元。 第二相关域包括具有第二高速缓冲存储器的第二处理单元。 在第一缓存存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为第一相关性状态。 响应于窥探专用访问请求，指定与地址标签匹配的目标地址，第一高速缓存存储器至少部分地基于第一相关性状态向独占访问请求提供第一部分响应。 响应于窥探专用访问请求，存储器控制器至少部分地基于确定的结果来确定它是否对目标地址负责并且向独占访问请求提供第二部分响应。 至少第一和第二部分响应被累积以获得专用访问请求的组合响应。 组合响应包括关于目标地址的家庭系统存储器的最高点的一致性和存储器控制器是否位于相同的一致性域内的指示。 响应于组合响应中的指示，第一缓存存储器将相关性状态字段从第一相关性状态更新为第二相关性状态。

    Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses
    56.
    发明申请
    Method and system for interfacing components of a computing system with a pair of unidirectional, point-to-point buses 失效
    用于将计算系统的组件与一对单向点对点总线接口的方法和系统

    公开(公告)号：US20070143511A1

    公开(公告)日：2007-06-21

    申请号：US11304474

    申请日：2005-12-15

    申请人： George Daly ,  James Fields ,  Donald Grice ,  Thomas Heller ,  Appoloniel Tankeh

    发明人： George Daly ,  James Fields ,  Donald Grice ,  Thomas Heller ,  Appoloniel Tankeh

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4269

    摘要： A method of interfacing two components of a computing system is provided wherein the method includes providing a pair of unidirectional, point-to-point buses to transmit data between a master bus controller of the computing system and a slave bus controller of a processor unit of the computing system. The method also includes providing means for transmitting a command packet with an address associated with data pertaining to the command from the master bus controller to the slave bus controller. In addition, the method includes providing means for determining by the slave bus controller whether the slave bus controller can accept the command. The method further includes providing means for transmitting an acknowledgement from the slave bus controller to the master bus controller after the slave bus controller receives a first signaling interval for the command packet if the slave bus controller can accept the command packet.

    摘要翻译： 提供了一种接口计算系统的两个组件的方法，其中所述方法包括提供一对单向点对点总线以在所述计算系统的主总线控制器与所述计算系统的总线控制器之间传送数据， 计算系统。 该方法还包括提供用于发送具有与从主总线控制器到从总线控制器的命令有关的数据相关联的地址的命令分组的装置。 此外，该方法包括提供用于由从总线控制器确定从总线控制器是否可以接受命令的装置。 该方法还包括提供用于在从总线控制器接收到命令分组之后从属总线控制器接收到用于命令分组的第一信令间隔的从总线控制器向主总线控制器发送确认的装置。

    Victim cache using direct intervention
    58.
    发明申请
    Victim cache using direct intervention 失效
    受害者缓存使用直接干预

    公开(公告)号：US20060184742A1

    公开(公告)日：2006-08-17

    申请号：US11056649

    申请日：2005-02-12

    申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  Bradley McCredie ,  William Starke

    发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  Bradley McCredie ,  William Starke

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0897 ,  G06F12/127

    摘要： A method, system, and device for enabling intervention across same-level cache memories. In a preferred embodiment, responsive to a cache miss in a first cache memory a direct intervention request is sent from the first cache memory to a second cache memory requesting a direct intervention that satisfies the cache miss. In an alternate embodiment, direct intervention is utilized to access a same-level victim cache.

    摘要翻译： 一种用于实现跨层级高速缓冲存储器的干预的方法，系统和设备。 在优选实施例中，响应于第一高速缓冲存储器中的高速缓存未命中，直接干预请求从第一高速缓存存储器发送到第二高速缓存存储器，请求满足高速缓存未命中的直接干预。 在替代实施例中，利用直接干预来访问相同级别的受害者缓存。

    Data processing system and method for predictively selecting a scope of broadcast of an operation
    60.
    发明申请
    Data processing system and method for predictively selecting a scope of broadcast of an operation 有权
    用于预测性地选择操作的广播范围的数据处理系统和方法

    公开(公告)号：US20060179241A1

    公开(公告)日：2006-08-10

    申请号：US11054886

    申请日：2005-02-10

    申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

    发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0844 ,  G06F12/0817 ,  G06F12/0831

    摘要： A cache coherent data processing system includes at least first and second coherency domains coupled for communication. The first and second coherency domains each include a respective one of first and second cache memories. A master in the first coherency domain selects a scope of an initial broadcast of an operation from among a first scope including only the first coherency domain and a second scope including both the first and second coherency domains based, at least in part, upon a type of the operation. The master then performs an initial broadcast of the operation within the cache coherent data processing system utilizing the selected scope.

    摘要翻译： 高速缓存一致数据处理系统至少包括耦合用于通信的第一和第二相干域。 第一和第二相关域各自包括第一和第二高速缓存存储器中的相应一个。 第一相关域中的主机至少部分地基于类型，从包括第一相关域的第一范围和包括第一和第二相干域两者的第二范围中选择操作的初始广播的范围 的操作。 然后，主机使用所选择的范围在高速缓存相干数据处理系统内执行操作的初始广播。