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    Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same
    51.
    发明申请
    Semiconductor memory device with MOS transistors, each including floating gate and control gate, and memory card including the same 失效
    具有MOS晶体管的半导体存储器件，各自包括浮动栅极和控制栅极，以及包括其的存储卡

    公开(公告)号：US20050237808A1

    公开(公告)日：2005-10-27

    申请号：US11111878

    申请日：2005-04-22

    申请人： Masaki Ichikawa ,  Takehiro Hasegawa ,  Akira Umezawa ,  Takuya Fujimoto

    发明人： Masaki Ichikawa ,  Takehiro Hasegawa ,  Akira Umezawa ,  Takuya Fujimoto

    IPC分类号： G11C16/04 ,  G11C11/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115

    摘要： A semiconductor memory device includes memory cells, a memory cell array, bit lines, source lines, word lines, and select gate lines. Each of the memory cells includes a first MOS transistor having a floating gate and a control gate and a second MOS transistor having a stacked gate including a first gate electrode and a second gate electrode formed above the first gate electrode and having its drain connected to the source of the first MOS transistor. Each of the bit lines electrically connects the drains of the first MOS transistors in a same column. Each of the word lines connects the control gates of the first MOS transistors in a same row. Each of the select gate lines electrically connects the second gate electrodes of the second MOS transistors in a same row and is electrically isolated from the second gate electrodes.

    摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，位线，源极线，字线和选择栅极线。 每个存储单元包括具有浮置栅极和控制栅极的第一MOS晶体管和具有堆叠栅极的第二MOS晶体管，所述堆叠栅极包括形成在第一栅极电极上方的第一栅电极和第二栅电极，并且其漏极连接到 第一MOS晶体管的源极。 每个位线在同一列中电连接第一MOS晶体管的漏极。 每个字线将第一MOS晶体管的控制栅极连接在同一行。 每个选择栅极线将第二MOS晶体管的第二栅极电连接在同一行中，并与第二栅极电隔离。

    Semiconductor memory device with reduced read time and power consumption
    52.
    发明授权
    Semiconductor memory device with reduced read time and power consumption 失效
    半导体存储器件具有减少的读取时间和功耗

    公开(公告)号：US5654912A

    公开(公告)日：1997-08-05

    申请号：US568500

    申请日：1995-12-07

    申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

    发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Hitoshi Kuyama

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/24

    CPC分类号： G11C11/4096 ,  G11C11/4045 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/103

    摘要： A semiconductor memory device comprises a memory array in which word lines are driven by a single decoder or a plurality of memory arrays driven by a plurality of decoders operating with the same row address, in the memory array or memory arrays memory cell units in which a plurality of memory cells are connected in series being arranged in the form of an array, a plurality of sense amplifier arrays constituted by arranging a plurality of sense amplifiers each provided for a pair of bit lines or a plurality of pairs of bit lines to read out data from the memory cells of the memory cell arrays, the sense amplifier arrays being divided into a plurality of blocks, and the blocks corresponding to one memory cell array, a register array having a plurality of registers for storing data read out by the plurality of sense amplifiers, the register array being divided into a plurality of blocks, and the blocks corresponding to the sense amplifier block and one memory cell array, and a control circuit for independently controlling the blocks of the sense amplifier arrays and the register array and independently reading out data from the registers in the blocks.

    摘要翻译： 半导体存储器件包括存储器阵列，其中字线由单个解码器驱动，或者由存储器阵列或存储器阵列存储单元单元中的由相同行地址操作的多个解码器驱动的多个存储器阵列驱动，其中， 多个存储单元以阵列的形式串联连接，多个读出放大器阵列通过布置多个读出放大器而构成，每个读出放大器分别设置用于一对位线或多对位线以读出 来自存储单元阵列的存储单元的数据，读出放大器阵列被划分为多个块，以及对应于一个存储单元阵列的块，具有多个寄存器的寄存器阵列，用于存储由多个块读出的数据 读出放大器，寄存器阵列被分成多个块，以及对应于读出放大器块和一个存储单元阵列的块，以及控制ci 用于独立控制读出放大器阵列和寄存器阵列的块，并独立地从块中的寄存器读出数据。