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33 条记录 (耗时 0.032 秒)

    Dynamic random access memory device
    5.
    发明授权
    Dynamic random access memory device 失效
    动态随机存取存储器

    公开(公告)号：US06295241B1

    公开(公告)日：2001-09-25

    申请号：US08251649

    申请日：1994-05-31

    申请人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

    发明人： Shigeyoshi Watanabe ,  Tsuneaki Fuse ,  Koji Sakui ,  Masako Ohta ,  Yukihito Oowaki ,  Kenji Numata ,  Fujio Masuoka

    IPC分类号： G11C702

    CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/14 ,  G11C11/4099

    摘要： Here is disclosed a dynamic semiconductor memory of high integration density, which has parallel word lines and parallel bit lines formed on a substrate. The bit lines include a pair of bit lines. A memory cell is coupled to a word line and to one bit line of the bit-line pair. The memory cell is composed of MOSFETs of a submicron size. A sense amplifier section is connected to the pair of bit lines, and senses and amplifies the potential difference between the pair of bit lines in a data readout mode. The amplifier section has a BIMOS structure, having MOSFETs and bipolar transistors. It has a driver section comprised of bipolar transistors.

    摘要翻译： 这里公开了具有高集成度密度的动态半导体存储器，其具有在基板上形成的并行字线和并行位线。 位线包括一对位线。 存储器单元耦合到字线和位线对的一个位线。 存储单元由亚微米尺寸的MOSFET组成。 读出放大器部分连接到一对位线，并且在数据读出模式下感测和放大一对位线之间的电位差。 放大器部分具有BIMOS结构，具有MOSFET和双极晶体管。 它具有由双极晶体管组成的驱动器部分。

    Semiconductor memory system with dynamic random access memory cells
    7.
    发明授权
    Semiconductor memory system with dynamic random access memory cells 失效
    具有动态随机存取存储单元的半导体存储器系统

    公开(公告)号：US4800530A

    公开(公告)日：1989-01-24

    申请号：US85086

    申请日：1987-08-13

    申请人： Yasuo Itoh ,  Fumio Horiguchi ,  Shigeyoshi Watanabe ,  Kazunori Ohuchi ,  Mitsugi Ogura

    发明人： Yasuo Itoh ,  Fumio Horiguchi ,  Shigeyoshi Watanabe ,  Kazunori Ohuchi ,  Mitsugi Ogura

    IPC分类号： G11C11/40 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/22 ,  G11C7/00 ,  G11C7/1033

    摘要： A dynamic random access memory system comprises first and second memory banks. A plurality of memory cells connected to a word line are grouped into first and second groups. The first group is arranged in the first memory bank and the second group is arranged in the second memory bank. Read/write means is provided in which each n bits from and to the first group and each n bits from and to the second group are read and written alternatively. Each bit is read and written in synchronism with the toggles of a column address strobe signal.

    摘要翻译： 动态随机存取存储器系统包括第一和第二存储体。 连接到字线的多个存储单元被分组为第一组和第二组。 第一组布置在第一存储体中，第二组布置在第二存储体中。 提供读/写装置，其中从第一组的每个n位和从第二组的每个n位和第二组的每个n位被交替地读取和写入。 每个位与列地址选通信号的切换同步读写。

    Semiconductor memory device having register groups for writing and reading data
    9.
    发明授权
    Semiconductor memory device having register groups for writing and reading data 失效
    具有用于写入和读取数据的寄存器组的半导体存储器件

    公开(公告)号：US5467303A

    公开(公告)日：1995-11-14

    申请号：US380443

    申请日：1995-01-30

    申请人： Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    发明人： Takehiro Hasegawa ,  Shigeyoshi Watanabe ,  Fujio Masuoka

    IPC分类号： G11C11/405 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4096 ,  G11C11/24 ,  G11C7/00

    CPC分类号： G11C11/4096 ,  G11C11/404

    摘要： A semiconductor memory device comprises an array of memory cell units, each of which has a plurality of MOS transistors connected in series and a plurality of information storage capacitors corresponding in number to the MOS transistors and each having its one end connected to the source of a corresponding one of the MOS transistors, and a plurality of register groups each of which is adapted to temporarily store information stored in one of the memory cell units for each column of the array in order to read from and write into each memory cell unit.

    摘要翻译： 半导体存储器件包括一组存储单元单元，每个存储单元单元具有串联连接的多个MOS晶体管和多个与MOS晶体管相对应的多个信息存储电容器，每个信号存储电容器的一端连接到 对应的一个MOS晶体管，以及多个寄存器组，每个寄存器组适于临时存储存储在阵列的每列的存储单元单元之一中的信息，以便从每个存储单元单元读取和写入。