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公开(公告)号：US07121679B2
公开(公告)日：2006-10-17
申请号：US10910700
申请日：2004-08-03
申请人： Takuya Fujimoto
发明人： Takuya Fujimoto
CPC分类号： B62J6/02 , F21L4/02 , F21Y2115/10
摘要： An illumination apparatus is provided that can achieve light distribution towards the front, and light illumination in a direction other than the front direction, without using a light source other than the light source for frontward illumination. The illumination apparatus includes a light emitting diode located at the front side of the illumination apparatus, corresponding to one end, a side transmission unit having a surface exposed at a gap in the casing, located rearward of the light emitting diode to transmit light from the side, and a light path modification unit, located rearward of the light emitting diode to modify the direction of light output from the light emitting diode towards the side transmission unit.
摘要翻译： 提供一种可以实现朝向前方的光分布以及除了前方向以外的方向的光照射的照明装置，而不使用除了用于向前照明的光源之外的光源。 照明装置包括位于照明装置的前侧的发光二极管，其对应于一端，侧面传输单元，其具有暴露在壳体中的间隙处的表面，位于发光二极管的后方以透射来自 以及位于发光二极管的后面的光路修改单元，以修改从发光二极管向侧向传输单元输出的光的方向。
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2.发明申请Semiconductor memory device having first and second memory cell arrays and a program method thereof 失效具有第一和第二存储单元阵列的半导体存储器件及其编程方法公开(公告)号：US20050270817A1
公开(公告)日：2005-12-08
申请号：US11075669
申请日：2005-03-10
申请人： Hideki Takeuchi , Takuya Fujimoto
发明人： Hideki Takeuchi , Takuya Fujimoto
CPC分类号： G11C16/10 , G11C29/789
摘要： A semiconductor memory device comprising: a first memory cell array including a plurality of memory cells, a first switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the first memory cell array, a latch circuit for latching the data transferred from the first switch circuit, a first write selector circuit for transferring the data transferred from the latch circuit, a first bit line connected to at least one of the plurality of memory cells and receiving the data transferred from the first write selector circuit, a second memory cell array including a plurality of memory cells that are different from the plurality of memory cells arranged in the first memory cell array, a second switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the second memory cell array, a second write selector circuit connected to the second switch circuit and transferring the data transferred from the second switch circuit, and a second bit line connected to at least one of the plurality of memory cells arranged in the second memory cell array.
摘要翻译： 一种半导体存储器件，包括：第一存储单元阵列，包括多个存储单元;第一开关电路，用于将被编程的数据传送到布置在第一存储单元阵列中的多个存储单元中的至少一个;锁存电路， 锁存从第一开关电路传送的数据，用于传送从锁存电路传送的数据的第一写选择器电路，连接到多个存储单元中的至少一个的第一位线，并接收从第一写选择器传送的数据 电路，包括与布置在第一存储单元阵列中的多个存储单元不同的多个存储单元的第二存储单元阵列;第二开关电路，用于将要编程的数据传送到多个存储单元中的至少一个存储单元 布置在第二存储单元阵列中的第二写选择器电路，连接到第二开关电路并传送数据转换 与第二开关电路错误，以及连接到布置在第二存储单元阵列中的多个存储单元中的至少一个的第二位线。
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公开(公告)号：US20050237842A1
公开(公告)日：2005-10-27
申请号：US11110715
申请日：2005-04-21
IPC分类号： G11C16/06 , G11C7/00 , G11C7/18 , G11C16/04 , G11C29/00 , G11C29/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C29/80 , G11C7/18 , G11C16/0433 , G11C29/789
摘要： A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.
摘要翻译： 一种半导体集成电路器件包括半导体存储器电路，其包括其中集成有正常单元的存储单元阵列和其中存储存储半导体存储器电路的操作信息的熔丝单元的熔丝电路。 熔丝单元是具有电荷存储层的单元晶体管和选择单元晶体管的选择晶体管的2晶体管型存储单元。
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4.发明申请Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same 有权包括浮动栅极和控制栅极的半导体存储器件，用于其的控制方法和包括其的存储卡公开(公告)号：US20050237824A1
公开(公告)日：2005-10-27
申请号：US11087576
申请日：2005-03-24
摘要： A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.
摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，字线，第一电荷泵电路和放电电路。 存储单元具有包括浮置栅极和控制栅极的堆叠栅极的第一MOS晶体管。 存储单元阵列包括排列成矩阵的存储单元。 字线通常连接在同一行中的第一MOS晶体管的控制栅极。 第一电荷泵电路被激活，并且在写入操作和擦除操作中产生第一电压。 第一电压供应阱区或字线。 放电电路当第一电荷泵电路被去激活时，将由第一电荷泵电路产生的电荷放电到地或电源电位，同时使电流流到第一电压的输出节点。
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公开(公告)号：US5675279A
公开(公告)日：1997-10-07
申请号：US667885
申请日：1996-06-20
申请人： Takuya Fujimoto , Yoshiharu Hirata
发明人： Takuya Fujimoto , Yoshiharu Hirata
IPC分类号： G11C11/407 , G11C16/06 , G11C17/00 , H02M3/00 , H02M3/07 , H03K17/06 , H03K3/01 , H03K19/094
CPC分类号： H02M3/073 , H03K17/063
摘要： A voltage stepup circuit having a plurality of setup circuit units connected in stages between an input voltage node and a stepup voltage node. Each circuit unit comprises at least two first and second MOS transistor T1 and T2. Each of first stepup capacitors is connected between a first clock signal supply node and a first connection node at which the drain and gate of a corresponding one of odd-numbered MOS transistors, of a plurality of MOS transistors connected in series through the plurality of stepup circuit units, are connected together. Each of second stepup capacitors is connected between a second connection node at which the drain and gate of a corresponding one of even-numbered MOS transistors of the plurality of MOS transistors connected together and a second clock signal supply node for supplying said second connection node with a second clock signal whose pulse width does not overlap in time with that of the first clock signal. A first clock amplitude control circuit limits the amplitude of the first clock signal to be supplied to the first clock signal supply node to a predetermined level and applies the first amplitude-limited clock signal to the first clock signal supply node. A second clock amplitude control circuit limits the amplitude of the second clock signal to be supplied to the second clock signal supply node to a predetermined level and applies the second amplitude-limited clock signal to the second clock signal supply node.
摘要翻译： 一种升压电路，具有在输入电压节点和升压电压节点之间分级连接的多个建立电路单元。 每个电路单元包括至少两个第一和第二MOS晶体管T1和T2。 第一升压电容器中的每一个连接在第一时钟信号供给节点和第一连接节点之间，多个MOS晶体管中的相应一个奇数MOS晶体管的漏极和栅极通过多个升压器串联连接 电路单元连接在一起。 每个第二升压电容器连接在连接在一起的多个MOS晶体管中的相应一个偶数MOS晶体管的漏极和栅极的第二连接节点和用于向所述第二连接节点提供所述第二连接节点的第二时钟信号供应节点 第二时钟信号的脉冲宽度与第一时钟信号的时间信号不重叠。 第一时钟幅度控制电路将要提供给第一时钟信号提供节点的第一时钟信号的幅度限制到预定电平，并将第一限幅时钟信号施加到第一时钟信号提供节点。 第二时钟幅度控制电路将要提供给第二时钟信号提供节点的第二时钟信号的幅度限制到预定电平，并将第二限幅时钟信号施加到第二时钟信号提供节点。
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公开(公告)号：US4918408A
公开(公告)日：1990-04-17
申请号：US284524
申请日：1988-12-15
CPC分类号： H03K3/014 , H03K3/0307
摘要： An oscillator including a CMOS inverter, a feedback reactance connected between the input and output terminals of the CMOS inverter and a CMOS transfer gate connected as a feedback resistor between the input and output terminals of the CMOS inverter, a power source terminal section to which an external voltage is applied, and a power control unit for converting the external voltage to a first internal voltage which is supplied as a power source voltage to the CMOS inverter. The power control unit converts the external voltage to a second internal voltage independently from the first internal voltage and supplies the second internal voltage as a gate control voltage to the CMOS transfer gate.
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公开(公告)号：US07342843B2
公开(公告)日：2008-03-11
申请号：US11110715
申请日：2005-04-21
IPC分类号： G11C17/18
CPC分类号： G11C29/80 , G11C7/18 , G11C16/0433 , G11C29/789
摘要： A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.
摘要翻译： 一种半导体集成电路器件包括半导体存储器电路，其包括其中集成有正常单元的存储单元阵列和其中存储存储半导体存储器电路的操作信息的熔丝单元的熔丝电路。 熔丝单元是具有电荷存储层的单元晶体管和选择单元晶体管的选择晶体管的2晶体管型存储单元。
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8.发明授权Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same 有权包括浮动栅极和控制栅极的半导体存储器件，用于其的控制方法和包括其的存储卡公开(公告)号：US07280407B2
公开(公告)日：2007-10-09
申请号：US11087576
申请日：2005-03-24
摘要： A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects commonly the control gates of the first MOS transistors in a same row. The first charge pump circuit is activated and generates a first voltage in a write operation and erase operation. The first voltage is supplied with either the well region or the word lines. The discharge circuit, when the first charge pump circuit is deactivated, discharges the charge generated by the first charge pump circuit to ground or to a power-supply potential, while causing current to flow to an output node of the first voltage.
摘要翻译： 半导体存储器件包括存储单元，存储单元阵列，字线，第一电荷泵电路和放电电路。 存储单元具有包括浮置栅极和控制栅极的堆叠栅极的第一MOS晶体管。 存储单元阵列包括排列成矩阵的存储单元。 字线通常连接在同一行中的第一MOS晶体管的控制栅极。 第一电荷泵电路被激活，并且在写入操作和擦除操作中产生第一电压。 第一电压供应阱区或字线。 放电电路当第一电荷泵电路被去激活时，将由第一电荷泵电路产生的电荷放电到地或电源电位，同时使电流流到第一电压的输出节点。
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公开(公告)号：US20070121335A1
公开(公告)日：2007-05-31
申请号：US11601187
申请日：2006-11-17
申请人： Takuya Fujimoto , Hiroshi Nakade
发明人： Takuya Fujimoto , Hiroshi Nakade
IPC分类号： F21V33/00
CPC分类号： B62J6/001 , B60Q1/1423 , B60Q2300/116 , B60Q2300/314 , B62J6/02
摘要： A headlamp for a bicycle includes an LED element, a power supply device supplying electric power to the LED element, a vibration sensor detecting vibration, a luminance detector detecting ambient illuminance, and a switching device providing ON-OFF control of electrical connection between the LED element and the power supply device in response to a result detected by the vibration sensor and a result detected by the illuminance detector. The vibration sensor has a helical spring and a central metal conductive wire passing through the helical spring, and the helical spring and the conductive wire are disposed to extend in a direction obliquely intersecting with a horizontal direction and a vertical direction when the headlamp is attached.
摘要翻译： 用于自行车的头灯包括LED元件，向LED元件提供电力的电源装置，检测振动的振动传感器，检测环境照度的亮度检测器以及提供LED之间的电连接的开 - 关控制的开关装置 元件和电源装置响应于由振动传感器检测到的结果和由照度检测器检测到的结果。 振动传感器具有螺旋弹簧和穿过螺旋弹簧的中心金属导线，并且螺旋弹簧和导线布置成当安装前照灯时沿与水平方向和垂直方向倾斜交叉的方向延伸。
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公开(公告)号：US20050047123A1
公开(公告)日：2005-03-03
申请号：US10910700
申请日：2004-08-03
申请人： Takuya Fujimoto
发明人： Takuya Fujimoto
IPC分类号： B62J6/02 , F21L4/00 , F21L4/02 , F21L4/04 , F21S2/00 , F21S8/10 , F21V7/04 , F21V8/00 , F21V11/00 , F21V13/00 , F21V13/04 , F21V14/00 , F21V23/04 , F21Y101/02
CPC分类号： B62J6/02 , F21L4/02 , F21Y2115/10
摘要： An illumination apparatus is provided that can achieve light distribution towards the front, and light illumination in a direction other than the front direction, without using a light source other than the light source for frontward illumination. The illumination apparatus includes a light emitting diode located at the front side of the illumination apparatus, corresponding to one end, a side transmission unit having a surface exposed at a gap in the casing, located rearward of the light emitting diode to transmit light from the side, and a light path modification unit, located rearward of the light emitting diode to modify the direction of light output from the light emitting diode towards the side transmission unit.
摘要翻译： 提供一种可以实现朝向前方的光分布以及除了前方向以外的方向的光照射的照明装置，而不使用除了用于向前照明的光源之外的光源。 照明装置包括位于照明装置的前侧的发光二极管，其对应于一端，侧面传输单元，其具有暴露在壳体中的间隙处的表面，位于发光二极管的后方以透射来自 以及位于发光二极管的后面的光路修改单元，以修改从发光二极管向侧向传输单元输出的光的方向。
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