公开(公告)号：US20210202407A1

公开(公告)日：2021-07-01

申请号：US16729488

申请日：2019-12-30

Applicant: Unimicron Technology Corp.

Inventor： John Hon-Shing Lau ,  Yu-Chi Shen ,  Tzyy-Jang Tseng ,  Chen-Hua Cheng ,  Pei-Wei Wang

IPC: H01L23/66 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01Q1/22

Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

公开(公告)号：US20210202394A1

公开(公告)日：2021-07-01

申请号：US17200892

申请日：2021-03-14

Applicant: Unimicron Technology Corp.

Inventor： Yi LIN ,  Chun-Ming CHIU ,  Hung-Chih LEE ,  Chang-Fu CHEN

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48

Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.

公开(公告)号：US20210195761A1

公开(公告)日：2021-06-24

申请号：US17194323

申请日：2021-03-08

Applicant: Unimicron Technology Corp.

Inventor： Kai-Ming YANG ,  Chen-Hao LIN ,  Wang-Hsiang TSAI ,  Cheng-Ta KO

IPC: H05K3/40 ,  H01L21/768 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18 ,  H05K1/14 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/36 ,  H01L23/538 ,  H05K3/46 ,  H01L23/00 ,  H01L21/683

Abstract: A package structure includes a metal layer, a composite layer of a non-conductor inorganic material and an organic material, a sealant, a chip, a circuit layer structure, and an insulating protective layer. The composite layer of the non-conductor inorganic material and the organic material is disposed on the metal layer. The sealant is bonded on the composite layer of the non-conductor inorganic material and the organic material. The chip is embedded in the sealant, and the chip has electrode pads. The circuit layer structure is formed on the sealant and the chip. The circuit layer structure includes at least one dielectric layer and at least one circuit layer. The dielectric layer has conductive blind holes. The insulating protective layer is formed on the circuit layer structure. The insulating protective layer has openings, so as to expose parts of the surface of the circuit layer structure in the openings.

公开(公告)号：US20210175160A1

公开(公告)日：2021-06-10

申请号：US16747548

申请日：2020-01-21

Applicant: Unimicron Technology Corp.

Inventor： Shih-Liang CHENG

IPC: H01L23/498 ,  H01L21/48

Abstract: A wiring board and a method of manufacturing the same are provided. The method includes the following steps. A substrate is provided. The substrate is perforated to form at least one through hole. A first conductive layer is integrally formed on a surface of the substrate and an inner wall of the through hole. An etch stop layer is formed on a portion of the first conductive layer on the surface of the substrate and another portion of the first conductive layer on the inner wall of the through hole. A second conductive layer is integrally formed on the etch stop layer and the first conductive layer on the inner wall of the through hole. A plug-hole column is formed by filling with a plugged-hole material in the through hole. The second conductive layer is removed. The etch stop layer is then removed.

公开(公告)号：US11032917B2

公开(公告)日：2021-06-08

申请号：US16503500

申请日：2019-07-04

Applicant: Unimicron Technology Corp.

Inventor： Wei-Ti Lin ,  Chun-Hsien Chien ,  Fu-Yang Chen

IPC: H05K7/10 ,  H05K3/46 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11

Abstract: A circuit carrier board includes a first substrate and a second substrate bonding to the first substrate. The first substrate includes a first circuit layer connecting to a plurality of conductive structure. The conductive structures connect to electronic elements. The second substrate contacts the first circuit layer. The second substrate includes a plurality of stacked dielectric layers, and a plurality of second circuit layers are disposed in the dielectric layers. The bottommost layer of the second circuit layers is exposed outside of the dielectric layers, and the topmost layer of the second circuit layers is electrically connected to the first circuit layer. The conductive structure includes a pad and a conductive via. The pad electrically connects to the first circuit layer. A linewidth of the first circuit layer is smaller than a linewidth of the second circuit layer. A manufacturing method of the circuit carrier board is also provided.

公开(公告)号：US20210118839A1

公开(公告)日：2021-04-22

申请号：US16687557

申请日：2019-11-18

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Ra-Min Tain ,  Tzyy-Jang Tseng

IPC: H01L23/00 ,  H01L23/538

Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

公开(公告)号：US10964634B2

公开(公告)日：2021-03-30

申请号：US16162396

申请日：2018-10-17

Applicant: Unimicron Technology Corp.

Inventor： Chien-Chen Lin ,  Tzu-Hsuan Wang ,  Kuan-Wen Fong

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

Abstract: A circuit carrier with embedded substrate includes a circuit structure and an embedded substrate. The circuit structure includes a first dielectric layer, a first patterned circuit layer, a trench, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is embedded in the first surface. The first bumps are disposed on the first surface and electrically connected to the first patterned circuit layer. The trench exposes a portion of the first dielectric layer. The embedded substrate is disposed in the trench and includes a plurality of second bumps. A chip package structure includes the above circuit carrier with embedded substrate.

公开(公告)号：US10957658B2

公开(公告)日：2021-03-23

申请号：US16866530

申请日：2020-05-04

Applicant: Unimicron Technology Corp.

Inventor： Pu-Ju Lin ,  Cheng-Ta Ko ,  Yu-Hua Chen ,  Tzyy-Jang Tseng ,  Ra-Min Tain

IPC: H01L23/16 ,  H01L23/66 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.

公开(公告)号：US20210082810A1

公开(公告)日：2021-03-18

申请号：US17095744

申请日：2020-11-12

Applicant: Industrial Technology Research Institute ,  Unimicron Technology Corp.

Inventor： Yu-Hua Chen ,  Wei-Chung Lo ,  Tao-Chih Chang ,  Yu-Min Lin ,  Sheng-Tsai Wu

IPC: H01L23/522 ,  H01L23/498 ,  H01L21/48 ,  H01L25/04

Abstract: A package substrate includes a substrate, an insulating protective layer and an interposer. The substrate has a first surface and a second surface opposing to the first surface. The substrate includes a plurality of first conductive pads embedded in the first surface. The insulating protective layer is disposed on the first surface of the substrate. The insulating protective layer has an opening for exposing the first conductive pads embedded in the first surface of the substrate. The interposer has a top surface and a bottom surface opposing to the top surface. The interposer includes a plurality of conductive vias and a plurality of second conductive pads located on the bottom surface. The interposer is located in a recess defined by the opening of the insulating protective layer and the first surface of the substrate. Each of the second conductive pads is electrically connected to corresponding first conductive pad.

公开(公告)号：US10950535B2

公开(公告)日：2021-03-16

申请号：US16785630

申请日：2020-02-09

Applicant: Unimicron Technology Corp.

Inventor： Chun-Min Wang ,  Pu-Ju Lin ,  Cheng-Ta Ko

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

Abstract: A package structure includes a redistribution structure, a chip, an inner conductive reinforcing element, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The inner conductive reinforcing element is disposed over the redistribution structure. The inner conductive reinforcing element has a Young's modulus in a range of from 30 to 200 GPa. The protective layer covers the chip and a sidewall of an opening of the inner conductive reinforcing element.