公开(公告)号：US11068639B2

公开(公告)日：2021-07-20

申请号：US16165675

申请日：2018-10-19

Applicant: Arm Limited

Inventor： Marlin Wayne Frederick, Jr. ,  Ettore Amirante ,  Ronald Paxton Preston ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong

IPC: G06F30/39 ,  G06F30/394 ,  G11C11/419 ,  G11C7/12

Abstract: Various implementations described herein refer to a method. The method may include providing a metal layout for an integrated circuit, wherein the metal layout includes multiple lines associated with bitlines. The method may include inserting at least one additional line between the multiple lines and the bitlines. The method may include arranging the at least one additional line with respect to the multiple lines and the bitlines so as to reduce capacitance associated with the bitlines.

公开(公告)号：US20210193195A1

公开(公告)日：2021-06-24

申请号：US16725779

申请日：2019-12-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Munish Kumar

IPC: G11C7/10

Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.

公开(公告)号：US10978141B1

公开(公告)日：2021-04-13

申请号：US16698851

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Vivek Asthana ,  Munish Kumar

IPC: G11C11/418 ,  G11C11/417 ,  G11C11/419

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry, two or more memory instances coupled to the first and second word-line decoder circuitry; and a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances. Also, a pin bus enabled in the control block circuitry may be configured to at least partially control selection of one or more of the two or more memory instances.

公开(公告)号：US20210065785A1

公开(公告)日：2021-03-04

申请号：US16555899

申请日：2019-08-29

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Pratik Ghanshambhai Satasia

IPC: G11C11/419 ,  G11C11/418 ,  H03K5/24

Abstract: Various implementations described herein are directed to a device having various circuitry for reading first data from a memory location in single-port memory and writing second data to the memory location in the single-port memory after reading the first data from the memory location. In some implementations, reading the first data and writing the second data to the memory location are performed in a single operation.

公开(公告)号：US10817420B2

公开(公告)日：2020-10-27

申请号：US16175151

申请日：2018-10-30

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen

IPC: G06F12/06 ,  G06F12/02

Abstract: A method for accessing two memory locations in two different memory arrays based on a single address string includes determining three sets of address bits. A first set of address bits are common to the addresses of wordlines that correspond to the memory locations in the two memory arrays. A second set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a first memory location in a first memory array. A third set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a second memory location in a second memory array. The method includes populating the single address string with the three sets of address bits and may be performed by an address data processing unit.

公开(公告)号：US10763267B2

公开(公告)日：2020-09-01

申请号：US16244047

申请日：2019-01-09

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Munish Kumar

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/419 ,  H01L23/528 ,  G11C11/418

Abstract: Various implementations described herein refer to an integrated circuit having a memory structure with a two-bitcell layout and a four cell poly pitch. The two-bitcell layout includes a first bitcell and a second bitcell with structural contours that are joined together in a coupling arrangement. The first bitcell and the second bitcell have multiple transistors that are arranged to store data during write operations and allow access of data during read operations.

公开(公告)号：US20200133850A1

公开(公告)日：2020-04-30

申请号：US16175151

申请日：2018-10-30

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen

IPC: G06F12/06 ,  G06F12/02

Abstract: A method for accessing two memory locations in two different memory arrays based on a single address string includes determining three sets of address bits. A first set of address bits are common to the addresses of wordlines that correspond to the memory locations in the two memory arrays. A second set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a first memory location in a first memory array. A third set of address bits concatenated with the first set of address bits provides the address of the wordline that corresponds to a second memory location in a second memory array. The method includes populating the single address string with the three sets of address bits and may be performed by an address data processing unit.

公开(公告)号：US09281027B1

公开(公告)日：2016-03-08

申请号：US14511581

申请日：2014-10-10

Applicant: ARM LIMITED

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Mudit Bhargava

IPC: G11C7/00 ,  G11C7/10

CPC classification number: G11C7/106 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/419 ,  G11C29/04

Abstract: A memory device includes latching circuitry for receiving a latching value and for providing said latching value as an output. A path receives said latching value and passes said latching value to said latching circuitry. First storage circuitry provides a first stored value when said memory device is in a read mode of operation. A bit line is connected to said first storage circuitry. First control circuitry selectively connects said bit line to said path. Sensing circuitry, when an enable signal is active, detects a voltage change on said path as a result of connecting said bit line to said first storage circuitry and said path, and outputs a latching value, dependent on said voltage change, on said path. Second storage circuitry provides a second stored value in a test mode of operation and second control circuitry receives said second stored value and selectively outputs said second stored value as said latching value on said path. Said latching circuitry outputs said latching value as said output in dependence on said enable signal, such that said enable signal controls both said latching circuitry and said sense circuitry.

Abstract translation: 存储器件包括用于接收锁存值并用于提供所述锁存值作为输出的锁存电路。 路径接收所述锁存值并将所述锁存值传递到所述锁存电路。 当所述存储器件处于读取操作模式时，第一存储电路提供第一存储值。 位线连接到所述第一存储电路。 第一控制电路选择性地将所述位线连接到所述路径。 感测电路，当使能信号有效时，由于将所述位线连接到所述第一存储电路和所述路径而检测所述路径上的电压变化，并根据所述电压变化在所述路径上输出锁存值。 第二存储电路在测试操作模式中提供第二存储值，第二控制电路接收所述第二存储值，并且有选择地将所述第二存储值输出作为所述路径上的锁存值。 所述锁存电路根据所述使能信号输出所述锁存值作为所述输出，使得所述使能信号控制所述锁存电路和所述检测电路。

公开(公告)号：US20240135988A1

公开(公告)日：2024-04-25

申请号：US17971226

申请日：2022-10-20

Applicant: Arm Limited

Inventor： Vianney Antoine Choserot ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

公开(公告)号：US20230136348A1

公开(公告)日：2023-05-04

申请号：US17515258

申请日：2021-10-29

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Yew Keong Chong ,  Munish Kumar ,  Andy Wangkun Chen ,  Rajiv Kumar Sisodia

IPC: G11C7/06 ,  G11C5/06 ,  G11C7/10

Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.