公开(公告)号：US20220318040A1

公开(公告)日：2022-10-06

申请号：US17219051

申请日：2021-03-31

Applicant: ATI Technologies ULC

Inventor： Sean T. White ,  Philip Ng

IPC: G06F9/455 ,  G06F12/0882 ,  G06F12/0811 ,  G06F12/06

Abstract: Methods and apparatus for providing page migration of pages among tiered memories identify frequently accessed memory pages in each memory tier and generate page hotness ranking information indicating how frequently memory pages are being accessed. Methods and apparatus provide the page hotness ranking information to an operating system or hypervisor depending on which is used in the system, the operating system or hypervisor issues a page move command to a hardware data mover, based on the page hotness ranking information and the hardware data mover moves a memory page to a different memory tier in response to the page move command from the operating system.

公开(公告)号：US11296905B2

公开(公告)日：2022-04-05

申请号：US16219149

申请日：2018-12-13

Applicant: ATI TECHNOLOGIES ULC

Inventor： Michael McLean ,  Philip Ng

IPC: H04L12/40 ,  G06F13/40 ,  H04L45/745 ,  H04L45/00

Abstract: A Management Component Transport Protocol platform management subsystem includes an internal bridge, a first segment group, and a second segment group. The first segment group is coupled to the internal bridge. The second segment group is coupled to the internal bridge and the first segment group. The first segment group has a first plurality of Peripheral Component Interconnect Express (PCIe)-based buses. The second segment group has a second plurality of PCIe-based buses, wherein based on an identification (ID)-routed packet from the first segment group to the second segment group, the internal bridge routes the ID-routed packet to the second segment group.

公开(公告)号：US20200097413A1

公开(公告)日：2020-03-26

申请号：US16141603

申请日：2018-09-25

Applicant: ATI Technologies ULC

Inventor： Nippon Harshadk Raval ,  Philip Ng

IPC: G06F12/1045

Abstract: Methods, devices, and systems for virtual address translation. A memory management unit (MMU) receives a request to translate a virtual memory address to a physical memory address and searching a translation lookaside buffer (TLB) for a translation to the physical memory address based on the virtual memory address. If the translation is not found in the TLB, the MMU searches an external memory translation lookaside buffer (EMTLB) for the physical memory address and performs a page table walk, using a page table walker (PTW), to retrieve the translation. If the translation is found in the EMTLB, the MMU aborts the page table walk and returns the physical memory address. If the translation is not found in the TLB and not found in the EMTLB, the MMU returns the physical memory address based on the page table walk.

公开(公告)号：US20250004494A1

公开(公告)日：2025-01-02

申请号：US18345985

申请日：2023-06-30

Applicant: ATI Technologies ULC

Inventor： Carlos Javier Moreira ,  Michael McLean ,  Philip Ng

IPC: G06F1/04

Abstract: The disclosed device includes an input/output (I/O) system clock configured to operate at one of a plurality of clock states and a control circuit configured to dynamically adjust a clock state of the I/O system clock. The control circuit can update an activity level of a current clock state based at least on I/O traffic activity and, in response to the activity level going beyond an activity range for the current clock state, transition the I/O system clock to a neighboring clock state. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US11567666B2

公开(公告)日：2023-01-31

申请号：US17211036

申请日：2021-03-24

Applicant: ATI Technologies ULC

Inventor： Philip Ng ,  Nippon Raval

IPC: G06F3/06

Abstract: An electronic device includes a memory, a processor that executes a software entity, a page migration engine (PME), and an input-output memory management unit (IOMMU). The software entity and the PME perform operations for preparing to migrate a page of memory that is accessible by at least one IO device in the memory, the software entity and the PME set migration state information in a page table entry for the page of memory and information in reverse map table (RMT) entries involved with migrating the page of memory based on the operations being performed. The IOMMU controls usage of information from the page table entry and controls performance of memory accesses of the page of memory based on the migration state information in the page table entry and information in the RMT entries. When the operations for preparing to migrate the page of memory are completed, the PME migrates the page of memory in the memory.

公开(公告)号：US20220308756A1

公开(公告)日：2022-09-29

申请号：US17214686

申请日：2021-03-26

Applicant: ATI Technologies ULC

Inventor： Nippon Raval ,  Philip Ng

IPC: G06F3/06

Abstract: An electronic device includes an input-output memory management unit (IOMMU). The IOMMU receives, from an input-output device, a memory access request directed to a given page of memory. The IOMMU then determines a particular encryption key from among a plurality of encryption keys associated with an owning entity to which the given page of memory is assigned. The IOMMU next communicates, to a encryption functional block, a specification of the particular encryption key to be used for encryption-related operations for processing the memory access request.

公开(公告)号：US11307904B2

公开(公告)日：2022-04-19

申请号：US16224378

申请日：2018-12-18

Applicant: ATI TECHNOLOGIES ULC

Inventor： Michael McLean ,  Philip Ng

IPC: G06F9/50 ,  G06F9/4401 ,  G06F15/78

Abstract: A system-on-chip (SOC), includes a memory, a partition access module coupled to the memory, a partition requesting unit coupled to the partition access module, and a first input-output (IO) device coupled to the partition access module. The partition access module creates a first partition of the SOC. The first partition includes a first portion of a first processor, the first IO device, and a first portion of the memory. Based upon a partition request, the partition access module repartitions the SOC to create a dynamic partition. The dynamic partition includes the first portion of the first processor, the first input-output (IO) device, the first portion of the memory, and a second IO device not included in the first partition.

公开(公告)号：US12210465B2

公开(公告)日：2025-01-28

申请号：US17145750

申请日：2021-01-11

Applicant: ATI Technologies ULC

Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

IPC: G06F13/16 ,  G06F9/455 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/1009

Abstract: An electronic device includes a processor that executes one or more guest operating systems and an input-output memory management unit (IOMMU). The IOMMU accesses, for/on behalf of each guest operating system among the one or more guest operating systems, IOMMU memory-mapped input-output (MMIO) registers in a separate copy of a set of IOMMU MMIO registers for that guest operating system.

公开(公告)号：US11886367B2

公开(公告)日：2024-01-30

申请号：US17545930

申请日：2021-12-08

Applicant: ATI Technologies ULC

Inventor： Michael E. McLean ,  Philip Ng

IPC: G06F13/372 ,  G06F13/364 ,  G06F9/48 ,  G06F13/40 ,  G06F13/366

CPC classification number: G06F13/372 ,  G06F9/4812 ,  G06F13/364 ,  G06F13/366 ,  G06F13/4059

Abstract: An arbitration system receives requests to access a destination during an arbitration window that spans multiple processor clock cycles. During each clock cycle, the destination is monitored to determine whether the destination is suffering from backpressure by receiving more requests than the destination is able to accommodate during the clock cycle. In response to detecting backpressure, a masking index value assigned to a requesting source is incremented, which limits an amount of requests from the source that will be granted destination access during a subsequent arbitration window. Alternatively, in response to detecting an absence of backpressure during an arbitration window, the masking index value is decremented, which increases the amount of requests from the source that will be granted destination access during a subsequent arbitration window. This arbitration process continues for successive arbitration windows, oscillating between incrementing and decrementing the masking index value during the successive arbitration windows.

公开(公告)号：US11243891B2

公开(公告)日：2022-02-08

申请号：US16141603

申请日：2018-09-25

Applicant: ATI Technologies ULC

Inventor： Nippon Harshadk Raval ,  Philip Ng

IPC: G06F12/00 ,  G06F12/1045

Abstract: Methods, devices, and systems for virtual address translation. A memory management unit (MMU) receives a request to translate a virtual memory address to a physical memory address and searching a translation lookaside buffer (TLB) for a translation to the physical memory address based on the virtual memory address. If the translation is not found in the TLB, the MMU searches an external memory translation lookaside buffer (EMTLB) for the physical memory address and performs a page table walk, using a page table walker (PTW), to retrieve the translation. If the translation is found in the EMTLB, the MMU aborts the page table walk and returns the physical memory address. If the translation is not found in the TLB and not found in the EMTLB, the MMU returns the physical memory address based on the page table walk.