公开(公告)号：US09323932B2

公开(公告)日：2016-04-26

申请号：US13720293

申请日：2012-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel

IPC: G06F21/57 ,  G06F21/78

CPC classification number: G06F21/575 ,  G06F21/78

Abstract: Embodiments include methods, systems, and computer storage devices directed to identifying that a trusted boot mode (TBM) control bit is set in an input/output memory management unit (IOMMU) and configuring the IOMMU to block a DMA request received by the IOMMU from a peripheral in response to the identifying.

Abstract translation: 实施例包括旨在识别在输入/输出存储器管理单元（IOMMU）中设置可信引导模式（TBM）控制位并且配置IOMMU以阻止由IOMMU接收的DMA请求的方法，系统和计算机存储设备 响应识别的外设。

公开(公告)号：US20150186240A1

公开(公告)日：2015-07-02

申请号：US14146565

申请日：2014-01-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew G. Kegel

IPC: G06F11/30

CPC classification number: G06F11/3051 ,  G06F11/3034 ,  G06F11/3065 ,  G06F11/3442 ,  G06F11/3476 ,  G06F12/02 ,  G06F12/0223 ,  G06F12/1081 ,  G06F17/40 ,  G06F2201/81 ,  G06F2212/1024 ,  G06F2212/1044 ,  G06F2212/502

Abstract: A method of managing peripherals is performed in a device coupled to a processor in a computer system. In the method, information associated with I/O activity for one or more peripherals is recorded in a first segment of a log. A second segment of the log is identified based on a next-segment pointer associated with the first segment of the log. In response to detecting a lack of available capacity in the first segment of the log, information associated with further I/O activity for the one or more peripherals is recorded in the second segment of the log.

Abstract translation: 在耦合到计算机系统中的处理器的设备中执行管理外围设备的方法。 在该方法中，与一个或多个外围设备的I / O活动相关联的信息被记录在日志的第一段中。 基于与日志的第一段相关联的下一段指针来识别日志的第二段。 响应于检测到日志的第一段中的可用容量的缺乏，与一个或多个外围设备的进一步I / O活动相关联的信息被记录在日志的第二段中。

公开(公告)号：US20140173236A1

公开(公告)日：2014-06-19

申请号：US13719671

申请日：2012-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew G. Kegel

IPC: G06F12/14

CPC classification number: G06F12/1441 ,  G06F12/1081 ,  G06F21/604 ,  G06F21/78

Abstract: A computer system is provided for preventing peripheral devices and/or processor cores from accessing restricted portions of system memory. For example, the computer system can include a host bridge, system memory coupled to the host bridge via a first access bus, a security processor coupled to the host bridge via a memory access bus that allows the security processor to access system memory and to access the peripheral device, and a security processor memory management unit (SPMMU) coupled between the peripheral device and the host bridge. The security processor is configured to program the SPMMU via the memory access bus to specify a first restricted range of physical addresses in the system memory that the peripheral device is not permitted to access. The SPMMU can then process access requests from the peripheral device and deny access requests that are determined to be within the first restricted range.

Abstract translation: 提供了一种用于防止外围设备和/或处理器核心访问系统存储器的限制部分的计算机系统。 例如，计算机系统可以包括主桥，经由第一访问总线耦合到主桥的系统存储器，经由存储器访问总线耦合到主桥的安全处理器，其允许安全处理器访问系统存储器并访问 外围设备和耦合在外围设备和主机桥之间的安全处理器存储器管理单元（SPMMU）。 安全处理器被配置为经由存储器访问总线对SPMMU进行编程，以指定外部设备不被允许访问的系统存储器中的物理地址的第一受限范围。 SPMMU然后可以处理来自外围设备的访问请求，并拒绝被确定在第一限制范围内的访问请求。

公开(公告)号：US20140101405A1

公开(公告)日：2014-04-10

申请号：US13645685

申请日：2012-10-05

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Misel-Myrto Papadopoulou ,  Lisa R. Hsu ,  Andrew G. Kegel ,  Nuwan S. Jayasena ,  Bradford M. Beckmann ,  Steven K. Reinhardt

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/4856 ,  G06F2212/654 ,  Y02D10/13 ,  Y02D10/24 ,  Y02D10/32

Abstract: Methods and apparatuses are provided for avoiding cold translation lookaside buffer (TLB) misses in a computer system. A typical system is configured as a heterogeneous computing system having at least one central processing unit (CPU) and one or more graphic processing units (GPUs) that share a common memory address space. Each processing unit (CPU and GPU) has an independent TLB. When offloading a task from a particular CPU to a particular GPU, translation information is sent along with the task assignment. The translation information allows the GPU to load the address translation data into the TLB associated with the one or more GPUs prior to executing the task. Preloading the TLB of the GPUs reduces or avoids cold TLB misses that could otherwise occur without the benefits offered by the present disclosure.

Abstract translation: 提供了用于避免计算机系统中冷翻译后备缓冲器（TLB）未命中的方法和装置。 典型的系统被配置为具有至少一个中央处理单元（CPU）和共享公共存储器地址空间的一个或多个图形处理单元（GPU）的异构计算系统。 每个处理单元（CPU和GPU）都有独立的TLB。 当将任务从特定CPU卸载到特定GPU时，将随任务分配一起发送翻译信息。 翻译信息允许GPU在执行任务之前将地址转换数据加载到与一个或多个GPU相关联的TLB中。 GPU的预加载减少或避免了在没有本公开提供的优点的情况下可能发生的冷TLB未命中。

公开(公告)号：US20140089609A1

公开(公告)日：2014-03-27

申请号：US13627895

申请日：2012-09-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Andrew G. Kegel ,  Gabriel H. Loh

IPC: H01L23/535 ,  G06F12/00 ,  H01L21/768

CPC classification number: H01L25/0652 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system is provided that includes an interposer having memory controller circuitry embedded therein. The interposer includes conductive vias that are embedded within and that extend through the interposer. The memory controller circuitry can be coupled to some of the conductive vias. In some implementations, other ones of the conductive vias are configured to be coupled to a processor and a memory module that can be mounted along a surface of the interposer. Conductive links are disposed on a surface of the interposer to couple the processor and the memory module to the memory controller circuitry.

Abstract translation: 提供了一种系统，其包括嵌入其中的存储器控​​制器电路的插入器。 插入器包括嵌入在插入件内并延伸穿过插入件的导电通孔。 存储器控制器电路可以耦合到一些导电通孔。 在一些实施方案中，导电通孔中的其它导电通孔被配置为耦合到处理器和可沿着插入器的表面安装的存储器模块。 导电链路设置在插入器的表面上，以将处理器和存储器模块耦合到存储器控制器电路。