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    Wave creation control with dynamic resource allocation
    51.
    发明授权
    Wave creation control with dynamic resource allocation 有权

    公开(公告)号：US10558499B2

    公开(公告)日：2020-02-11

    申请号：US15794593

    申请日：2017-10-26

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Maxim V. Kazakov ,  Michael Mantor

    IPC: G06F9/50

    Abstract: Footprints, or resource allocations, of waves within resources that are shared by processor cores in a multithreaded processor are measured concurrently with the waves executing on the processor cores. The footprints are averaged over a time interval. A number of waves are spawned and dispatched for execution in the multithreaded processor based on the average footprint. In some cases, the waves are spawned at a rate that is determined based on the average value of the footprints of waves within the resources. The rate of spawning waves is modified in response to a change in the average value of the footprints of the waves within the resources.

    Graphics processing hardware for using compute shaders as front end for vertex shaders
    52.
    发明授权
    Graphics processing hardware for using compute shaders as front end for vertex shaders 有权

    公开(公告)号：US10134102B2

    公开(公告)日：2018-11-20

    申请号：US14297290

    申请日：2014-06-05

    Applicant: Sony Interactive Entertainment Inc. ,  Advanced Micro Devices, Inc.

    Inventor： Mark Evan Cerny ,  David Simpson ,  Jason Scanlin ,  Michael Mantor

    IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60

    Abstract: A GPU is configured to read and process data produced by a compute shader via the one or more ring buffers and pass the resulting processed data to a vertex shader as input. The GPU is further configured to allow the compute shader and vertex shader to write through a cache. Each ring buffer is configured to synchronize the compute shader and the vertex shader to prevent processed data generated by the compute shader that is written to a particular ring buffer from being overwritten before the data is accessed by the vertex shader. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

    MEMORY PROTECTION IN HIGHLY PARALLEL COMPUTING HARDWARE
    53.
    发明申请
    MEMORY PROTECTION IN HIGHLY PARALLEL COMPUTING HARDWARE 审中-公开

    公开(公告)号：US20180314579A1

    公开(公告)日：2018-11-01

    申请号：US15582443

    申请日：2017-04-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Carlos Sampayo ,  Michael Mantor

    IPC: G06F11/07 ,  G06F9/38

    CPC classification number: G06F11/1048 ,  G06F9/3865

    Abstract: Techniques for handling memory errors are disclosed. Various memory units of an accelerated processing device (“APD”) include error units for detecting errors in data stored in the memory (e.g., using parity protection or error correcting code). Upon detecting an error considered to be an “initial uncorrectable error,” the error unit triggers transmission of an initial uncorrectable error interrupt (“IUE interrupt”) to a processor. This IUE interrupt includes information identifying the specific memory unit in which the error occurred (and possible other information about the error). A halt interrupt is generated and transmitted to the processor in response to the data having the error being consumed (i.e., used by an operation such as an instruction or command), which causes the APD to halt operations. If the data having the error is not consumed, then the halt interrupt is never generated (that the error occurred may remain logged, however).

    HIERARCHICAL WORK SCHEDULING
    57.
    发明申请
    HIERARCHICAL WORK SCHEDULING 有权

    公开(公告)号：US20250068464A1

    公开(公告)日：2025-02-27

    申请号：US18940931

    申请日：2024-11-08

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

    IPC: G06F9/48

    Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

    STREAMING WAVE COALESCER CIRCUIT
    58.
    发明申请
    STREAMING WAVE COALESCER CIRCUIT 有权

    公开(公告)号：US20250068429A1

    公开(公告)日：2025-02-27

    申请号：US18536982

    申请日：2023-12-12

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： John Stephen Junkins ,  Christopher J. Brennan ,  Ian Richard Beaumont ,  Kellie Marks ,  Matthaeus G. Chajdas ,  Max Oberberger ,  Michael John Bedy ,  Michael Mantor ,  Sean Keely

    IPC: G06F9/38

    Abstract: A Streaming Wave Coalescer (SWC) circuit stores a first set of state values associated with a first subset of threads of a first wave in a bin based on each of the first subset of threads including a first set of instructions to be executed. A second set of state values associated with a second subset of threads of a second wave is stored in the bin based on each of the second subset of threads including the first set of instructions to be executed and based on the first wave and the second wave both being associated with a hard key. A third wave is formed from the threads of the first subset and the second subset and is emitted for execution. As a result of reorganizing the threads and reconstituting a different wave, thread divergence of waves sent for execution is reduced.

    Processing unit with small footprint arithmetic logic unit
    59.
    发明授权
    Processing unit with small footprint arithmetic logic unit 有权

    公开(公告)号：US12217021B2

    公开(公告)日：2025-02-04

    申请号：US18219268

    申请日：2023-07-07

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Bin He ,  Shubh Shah ,  Michael Mantor

    IPC: G06F7/57 ,  G06F17/16 ,  G06N3/08

    Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.

    ADAPTIVE MULTIMODAL FUSING FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION
    60.
    发明申请
    ADAPTIVE MULTIMODAL FUSING FOR NON-PLAYER CHARACTER GENERATION AND CONFIGURATION 有权

    公开(公告)号：US20240424407A1

    公开(公告)日：2024-12-26

    申请号：US18749065

    申请日：2024-06-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Karthik Mohan Kumar ,  Michael Mantor ,  Pedro Antonio Pena ,  Archana Ramalingam

    IPC: A63F13/67 ,  G06F40/284

    Abstract: Systems and techniques for generating and animating non-player characters (NPCs) within virtual digital environments are provided. Multimodal input data is received that comprises a plurality of input modalities for interaction with an NPC having a set of body features and a set of facial features. The multimodal input data is processed through one or more neural networks to generate animation sequences for both the body features and facial features of the NPC. Generating such animation sequences includes disentangling the multimodal input data to generate substantially disentangled latent representations, combining these representations with the multimodal input data, and using a large-language model (LLM) to generate speech data for the NPC. Further processing using reverse diffusion generates face vertex displacement data and joint trajectory data based on the combined representation and generated speech data. The face vertex displacement data, joint trajectory data, and speech data are used to produce an animated representation of the NPC, which is then provided to environment-specific adapters to animate the NPC within a virtual digital environment.

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